The VHDL code for the Cross Bar Switch is intended as a reference and should be properly simulated for timing and functionality before using it in a real-world design.

Description of the 32 x 32 Cross Bar Switch Test Bench    8-27-98

The testbench is the VHDL code to test the VHDL design for a 2 chip
design.  When combined together (see Visio diagram in file 
32x32x2chips.vsd and block diagram of operation 32x16xbar.vsd) the
two chips take any of the 32 inputs and place them on any combinations
of outputs.  ONLY one input per output.

The VHDL program testbench1.vhd takes two xbar blocks and combines 
them to get a 32 input, 32 output cross bar switch.  The VHDL
components required are xbar.vhd, enlogic.vhd, channel.vhd, dec16.vhd,
mux32.vhd, and d_latchs.vhd.  
The main signals of testbench1.vhd are:

chip0 - selects if chip is chip0 (chip0 = 1) or chip1 (chip0 = 0)
cs - controls function of the chips (chip select)
glbrst - global reset of all latches for start up or restart
res - reset - asynchronous signal that sets all outputs to channel 0
ts - tristate select - 1 = high impedance, 0 = output enable
cnf - loads all muxs with registers
load - loads the select registers with isl
isl (4 downto 0) - input select lines
osl (4 downto 0) - output select lines 
input (31 downto 0) - cross bar input
output (31 downto 0) - cross bar output

Run testbench1 on view logic for 45000 ns to see all the functions.
If you arrange the signal is the order above, it is easier to read
the waves generated by Vwaves.

The line chip0 is set to 1.  It is inverted into chip 1 in testbench1 
to set a zero for chip 1.

Description of time sequence:

0 - 200 ns global reset sequecne.
Set all latches to zero.  
See output go from all Z's to all 0's

400 - 7000 ns loading sequence.  
The input select lines are run from 0 to 31 in binary.  
The output select lines are run from 31 to 0 in binary.
Loading takes place in the middle of each binary count.  Each count
is 200 ns.  Loading in the middle is due to latches being used 
instead of flip-flops.  This is done to prevent information coming in
on the end of the loading signal.
At 6800, the cnf line loads all info into the muxs and you see the
output go from all 0's to having some Z's in it.  This is due to the
tristating of several inputs.  The tristate lines should stay at Z 
until they are reprogrammed.

7500 - 13700 ns input sequence.
The input lines shift a 1 from bit 31 to 0.  
The output follows the input in reverse order.  
Notice that the Z's never change.

14900 - 22500 ns reset without ts sequence.
At 14.9 us the reset line goes high.  
All the outputs are now programmed to show channel 0.  
Channel 0 has a 1 on it so all output lines show a 1.
The input lines shift a 1 from bit 31 to 0 to show that the output 
only follows input line 0.
Notice that when the tristate line goes high at 21 us, the output does
not change until the next reset at 22.5 us occurs.

22500 - 30000 ns reset with ts sequence
At 22.5 us, the reset line goes high again.  
The tristate line is high, so all outputs are set to high impedance Z.
The input lines shift a 1 from bit 31 to 0 to show that all lines stay
at Z.

31000 - 37600 ns Loading sequence
The isl lines are set to vector 00111 and the output lines are set to
vector 00000.
The ouput select lines change twice for every change in the input 
select line.
This programs output line 0 and 1 with input line 7 (00111), 
output line 2 and 3 with 01000, and so on up to output line 30 and 31
with input line 10110.
The loading sequence is the same, occurs in the middle of each of 
the selections.
At 37.5 us, the cnf line goes high loading all muxs.
Notice all output lines change to all 0's since the output lines 
programmed have no 1's in thier corresponding input.

38500 - 44500 ns Input sequence.
A 1 is shifted from input lines bit 0 to 31.  
The output lines show the corresponding 11 when the input line gets 
a one in input line 7 (00111) to input line 23 (10110).

End.

This test file helps show the functionallity of the cross bar switch.
It does not show every single possibility, but shows how the switch 
can be programmed, reset, tristated.  
Not all the output channes have to be programmed at one time.  
Blocks of 8 or 16 or just 1 can be done.  It all depends
on how you use the load and cnf lines.  

Warnings: Be careful the load line shuts of before you change the isl, 
or you could get a glitch.

Dan Young
Lattice Applications
8-27-98