                               FPGA LOADER Interface Reference Design
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File List
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1) ./docs/FPGA_LOADER_readme.txt                                                 --->readme file
   ./docs/FPGA_LOADER.pdf 		                                         --->reference design document

2) ./project/<language>/<project_name>.lpf                                       --->Constraint file is for V-BY-ONE board FPGA LOADER and it has to be modified according into the requirement

3) ./simulation/<language>/<loader_functional_timing_sim.do>.do                  --->Scripts for RTL simulation using AHDL

4) ./source/vhdl/flash_prog_load16_sp.vhd                                        --> Source files of vhdl version for fpga loader                
   ./source/verilog/flash_prog_load16_sp.v                                       --> Source files of verilog version for fpga loader
   ./source/ipexpress/verilog/loader_pll.v                                       --> Verilog Source files for PLL instantiation
   ./source/ipexpress/vhdl/loader_pll.vhd                                        --> VHDL Source files for PLL instantiation                       
   ./target/<language>/FLASH_PROGRAMMER.ngo                                      --> ngo file for FLASH Programmer 
   ./target/<language>/FLASH_PROGRAMMER_XO.ngo                                   --> ngo file for FLASH Programmer using XO
   ./target/<language>/FLASH_PROGRAMMER_ECP2.ngo                                 --> ngo file for FLASH Programmer using ECP2
   ./target/<language>/FLASH_PROGRAMMER_XP2.ngo                                  --> ngo file for FLASH Programmer using XP2
   ./target/<language>/FLASH_PROGRAMMER_XO2.ngo                                  --> ngo file for FLASH Programmer using XO2

5) ./testbench/<language>/<flash_prog_load16_sp_TB>                              -->Testbench for FPGA loader
   ./testbench/<language>/flash_model.vhd                                        -->VHDL version FLASH model

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!!IMPORTANT NOTES:!!
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1. Unzip the AN8077_Parallel_Flash_Programming_and_FPGA_Configuration.zip file using the existing folder names


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Using Diamond Software
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HOW TO CREATE A PROJECT IN DIAMOND:
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1. Launch Diamond 2.1 and above, in the GUI, select "File -> New Project", click Next
2. In the New Project popup, select the Project location as (./AN8077_Parallel_Flash_Programming_and_FPGA_Configuration/project/<language>)and provide a Project name and implementation 
   name and click Next.
3. Add the necessary source files from the directories "AN8077_Parallel_Flash_Programming_and_FPGA_Configuration/source/src/<language>"
    
    To use Verilog soucre code:

   ./source/rtl/verilog/flash_prog_load16_sp.v
   ./source/ipexpress/verilog/loader_pll.v
  
    To use VHDL soucre code:

   ./source/rtl/VHDL/flash_prog_load16_sp.vhd
   ./source/ipexpress/vhdl/loader_pll.vhd

   and click Next

4. Select the desired part and speedgrade:
5. Click Finish. Now the project is successfully created. 
6. Use "Project -> Set Top-Level Unit" to select the right top-level unit:
7. MAKE SURE the provided lpf ( <design_name>.lpf ) files are for the V-BY-ONE reference board and it has to be modified according into your requirement. 

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HOW TO RUN PLACE AND ROUTE IN DIAMOND
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0. MAKE SURE the project has been created before
1. Launch Diamond
2. In the "Start Page" window, click [Project\Open...], and select the project file (ldf format)
3. Double click on "Export Files/Bitstream File" in the "Process" window 


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HOW TO RUN FUNCTION SIMULATION UNDER DIAMOND:
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# To successfully run this script, make the following change:
# 1. change the directory "<User Directory Path>\AN8077_Parallel_Flash_Programming_and_FPGA_Configuration\simulation\<language>" with your directory path.


0. Run the implementation flow till the map to get.vo for verilog & .vho for vhdl file (this can be find in this directory./AN8077_Parallel_Flash_Programming_and_FPGA_Configuration/project/<language>) and paste this in simulation folder (./AN8077_Parallel_Flash_Programming_and_FPGA_Configuration/simulation/<language>)
   and copy this .vo name into the loader_functional_timing_sim.do line 14 of *.do script file. For timing simulation *.vo | *.vho file has to be generated from the "Export Files" option, after running the "PAR" and *.sdf file has to be placed in the directory ./AN8077_Parallel_Flash_Programming_and_FPGA_Configuration/simulation/<language>.
	
   Note: 1. There is a default *.vo & *.vho  files (./AN8077_Parallel_Flash_Programming_and_FPGA_Configuration/simulation/<language>) this can use be used for simulation, above procedure has to be followed if design has to regenerated for some other device.
	    this is for functional simulation only.
         2. For timing simulation *.vo or *.vho generated after running PAR has to be used in place of existing *.vo or *.vho file in the *.do script file  and line 17 of *.do file has to be commented and line 19 to be uncommented!.

1. Open the Aldec HDL click tools-->Excute macro and select the *.do script files from the respective language (AN8077_Parallel_Flash_Programming_and_FPGA_Configuration\simulation\<language>) folder.

2. Simulation result checking:
   a) For the FPGA loader testing only FPGA Configuration portion of the simulation is shown, that means configuration data which goes out of the LOADER to ECP3,here you 
      should be able to see some activity on the configuration databus (Data on the bus D[7:0] with respect to CCLK) before DONE pin goes HIGH


