-PLL in delay mode. No delay, no multiplier
-Tied mclk to fb. Nulls out delay of path to Primary resources.
-Added separate output and input buffer to mclk feedback delay path 
 (should use bi-di, bug there is a bug in Foundry). This nulls input
 buffer to pll and delay of output buffer of Output FF.
-Using FBEXTPDEL preference with 0ns delay . This will make the output
 buffer connected to the input buffer look like a bidi delay.
-Add DEL3 property to fb in pll. Will add 2 ns to fb delay path.
-Track feedback compensation through INPUT_SETUP and CLOCK_TO_OUT
 preferences.
-Delaying clock to Input flip flop in order to meet input setup time
 that was put out of spec when fb time increased. Using DEL3 (2ns). 
 Added this delay in epic on  ncd file from map. Will not need to do 
 this when cycle stealing works automatically.

