Place and Route Report

PAR: Place And Route ispLever_v50_Production_Build (40).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.
Mon May 09 17:53:53 2005

C:/ispTOOLS/ispfpga\bin\nt\par -f ddr_vhdl_pnr.p2t ddr_vhdl_pnr_map.ncd
ddr_vhdl_pnr.dir ddr_vhdl_pnr.prf

Preference file: ddr_vhdl_pnr.prf.

Cost Table Summary
Level/ Number Timing Run NCD
Cost [ncd] Unrouted Score Time Status
---------- -------- -------- ----- ------------
5_17 * 0 0 01:40 Complete
5_7 0 11 01:39 Complete
5_5 0 16 01:38 Complete
5_16 0 23 01:46 Complete
5_6 0 46 01:37 Complete
5_15 0 135 01:49 Complete
5_1 0 171 01:42 Complete
5_14 0 192 01:43 Complete
5_13 0 708 01:48 Complete
5_9 0 719 01:44 Complete
5_2 0 811 01:45 Complete
5_11 0 1042 01:52 Complete
5_4 0 1107 01:28 Complete
5_12 0 1501 01:53 Complete
5_3 0 1748 01:41 Complete
5_8 0 1963 01:43 Complete
5_10 0 4448 01:57 Complete

* : Design saved.

par done!
Lattice Place and Route Report for Design "ddr_vhdl_pnr_map.ncd"
Mon May 09 18:21:43 2005

Best Par Run
PAR: Place And Route ispLever_v50_Production_Build (40).
Command line: C:/ispTOOLS/ispfpga\bin\nt\par -f ddr_vhdl_pnr.p2t ddr_vhdl_pnr_map.ncd
ddr_vhdl_pnr.dir ddr_vhdl_pnr.prf
Preference file: ddr_vhdl_pnr.prf.
Placement level-cost: 5-17.
Routing Iterations: 6

Loading design for application par from file
C:/DOCUME~1/jhsin/LOCALS~1/Temp/neo_31.
"ddr_top" is an NCD, version 3.0, vendor LATTICE, device LFEC20E,
package FPBGA672, speed 5
Package: Version 1.8, Status: PRODUCTION
Speed Hardware Data: version 1.119
Device utilization summary:

PIO 130/400 32% used
130/400 32% bonded

IOLOGIC 63/400 15% used
DQS 2/24 8% used
DQSDLL 1/2 50% used
SLICE 1020/9856 10% used

GSR 1/1 100% used
PLL3 1/4 25% used

Number of Signals: 2470
Number of Connections: 6709
The following 3 signals are selected to use the primary clock routing resources:
pll_clk (driver: U1_ddr_sdram_mem_top/U1_kbar_clk_pll/U1_PLL, clk load #: 816)
U1_ddr_sdram_mem_top/kbar_clk (driver: U1_ddr_sdram_mem_top/U1_kbar_clk_pll/U1_PLL, clk load #: 43)
clk_in_c (driver: clk_in, clk load #: 14)

The following 1 signal is selected to use the DCS clock routing resource:
clk_in_c (driver: clk_in, clk load #: 14)

WARNING - par: Primary clock driver 'clk_in' is located at F6 (not a
dedicated clock PIO). Please check if user already located this
comp, or this comp has dedicated connection with PLLs which must
be placed at its corresponding dedicated PIOs.
The following 1 signal is selected to use the secondary clock routing resource:
rst_n_c (driver: rst_n, clk load #: 0, sr load #: 664, ce load #: 0)

WARNING - par: Secondary clock driver 'rst_n' is located at K1 (not a
dedicated clock PIO). Please check if user already located this
comp, or this comp has dedicated connection with PLLs which must
be placed at its corresponding dedicated PIOs.
Signal rst_n_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...............
Finished Placer Phase 0. REAL time: 9 secs

Starting Placer Phase 1.
Placer score = 671074.
...............................................
.........
Placer score = 411331.
Finished Placer Phase 1. REAL time: 1 mins 10 secs

Starting Placer Phase 2.
.
Placer score = 405243
Finished Placer Phase 2. REAL time: 1 mins 17 secs

Total placer CPU time: 1 mins 15 secs

Dumping design to file ddr_vhdl_pnr.dir/5_17.ncd.

0 connections routed; 6711 unrouted.
Starting router resource preassignment
WARNING - par: The driver of dcs clock net clk_in_c is not placed on one of
the PIO sites which are dedicated for primary clocks. This dcs
clock will be routed through general routing resource and may
suffer from excessive delay or skew.
WARNING - par: The driver of secondary clock net rst_n_c is not placed on
one of the PIO sites which are dedicated for secondary clocks.
This secondary clock will be routed through general routing
resource and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 1 mins 27 secs
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
6711 successful; 0 unrouted; (38) real time: 1 mins 37 secs
Dumping design to file ddr_vhdl_pnr.dir/5_17.ncd.
End of iteration 2
6711 successful; 0 unrouted; (0) real time: 1 mins 38 secs
Dumping design to file ddr_vhdl_pnr.dir/5_17.ncd.
Constraints are met.
Total CPU time 1 mins 30 secs
Total REAL time: 1 mins 38 secs
Completely routed.
End of route. 6711 routed (100.00%); 0 unrouted.
Checking DRC ...
No errors found.
Timing score: 0

Total REAL time to completion: 1 mins 40 secs

All signals are completely routed.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.

Generated from the file 'C:\EVALUATION BOARDS\EC\HIGH_END\EVAL_CODE\DDR\VHDL\PNR\ddr_vhdl_pnr.par'