--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v50_SP1_Build (17)
Thu Jun 23 11:37:18 2005
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr ddr_vhdl_pnr.ncd ddr_vhdl_pnr.prf
Design file: ddr_vhdl_pnr.ncd
Preference file: ddr_vhdl_pnr.prf
Device,speed: LFXP10C,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "pll_clk" 167.000000 MHz (0 errors)
4096 items scored, 0 timing errors detected.
Report: 170.184MHz is the maximum frequency for this preference.
FREQUENCY NET "clk_in_c" 40.000000 MHz (0 errors)
181 items scored, 0 timing errors detected.
Report: 251.383MHz is the maximum frequency for this preference.
BLOCK PATH FROM PORT "rst_n" (0 errors)
64 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "pll_clk" 167.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.112ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/flop_addr_d_11 (from pll_clk +)
Destination: FF Data in U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_row_1 (to pll_clk +)
Delay: 5.696ns (41.8% logic, 58.2% route), 8 logic levels.
Constraint Details:
5.696ns physical path delay SLICE_513 to SLICE_895 meets
5.988ns delay constraint less
0.000ns skew and
0.180ns M_SET requirement (totaling 5.808ns) by 0.112ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.342 R18C27C.CLK to R18C27C.Q1 SLICE_513 (from pll_clk)
ROUTE 4 1.395 R18C27C.Q1 to R20C29A.B0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/flop_addr_dZ0Z_11
B0TOFCO_DE --- 0.726 R20C29A.B0 to R20C29A.FCO SLICE_21
ROUTE 1 0.000 R20C29A.FCO to R20C29B.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq1_0_n
FCITOFCO_D --- 0.103 R20C29B.FCI to R20C29B.FCO SLICE_35
ROUTE 1 0.000 R20C29B.FCO to R20C29C.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq3_2_n
FCITOFCO_D --- 0.103 R20C29C.FCI to R20C29C.FCO SLICE_34
ROUTE 1 0.000 R20C29C.FCO to R20C29D.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq5_4_n
FCITOFCO_D --- 0.103 R20C29D.FCI to R20C29D.FCO SLICE_33
ROUTE 1 0.000 R20C29D.FCO to R20C30A.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq7_6_n
FCITOFCO_D --- 0.103 R20C30A.FCI to R20C30A.FCO SLICE_32
ROUTE 1 0.000 R20C30A.FCO to R20C30B.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq9_8_n
FCITOCOUT_ --- 0.603 R20C30B.FCI to R20C30B.OFX1 SLICE_31
ROUTE 1 1.123 R20C30B.OFX1 to R19C25C.D0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq11_10_n
CTOF_DEL --- 0.300 R19C25C.D0 to R19C25C.F0 SLICE_576
ROUTE 2 0.795 R19C25C.F0 to R20C25A.M0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/N_882_iZ0 (to pll_clk)
--------
5.696 (41.8% logic, 58.2% route), 8 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
2.622ns PLL3_R27C1.CLKOP to R18C27C.CLK
Destination Clock :
Delay Connection
2.622ns PLL3_R27C1.CLKOP to R20C25A.CLK
Report: 170.184MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk_in_c" 40.000000 MHz ;
181 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 21.022ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q wait_200us_count15_14_F2 (from M5GDCS10_clk_in_c +)
Destination: FF Data in waited_200us (to M5GDCS10_clk_in_c +)
Delay: 3.849ns (32.3% logic, 67.7% route), 4 logic levels.
Constraint Details:
3.849ns physical path delay SLICE_58 to SLICE_845 meets
25.000ns delay constraint less
0.000ns skew and
0.129ns DIN_SET requirement (totaling 24.871ns) by 21.022ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.342 R11C35D.CLK to R11C35D.Q1 SLICE_58 (from M5GDCS10_clk_in_c)
ROUTE 2 1.668 R11C35D.Q1 to R12C35C.A0 wait_200us_count_15
CTOF_DEL --- 0.300 R12C35C.A0 to R12C35C.F0 SLICE_935
ROUTE 1 0.355 R12C35C.F0 to R12C35C.C1 G_2_19_bmZ0
CTOF_DEL --- 0.300 R12C35C.C1 to R12C35C.F1 SLICE_935
ROUTE 1 0.584 R12C35C.F1 to R12C34C.C0 G_2Z0Z_19
CTOF_DEL --- 0.300 R12C34C.C0 to R12C34C.F0 SLICE_845
ROUTE 1 0.000 R12C34C.F0 to R12C34C.DI0 GZ0Z_1 (to M5GDCS10_clk_in_c)
--------
3.849 (32.3% logic, 67.7% route), 4 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
0.460ns URDCS0.DCSOUT to R11C35D.CLK
Destination Clock :
Delay Connection
0.460ns URDCS0.DCSOUT to R12C34C.CLK
Report: 251.383MHz is the maximum frequency for this preference.
================================================================================
Preference: BLOCK PATH FROM PORT "rst_n" ;
64 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: Port Pad rst_n
Destination: DQSDLL Port U1_ddr_sdram_mem_top/U1_DQSDLL (to pll_clk +)
Delay: 7.635ns (11.4% logic, 88.6% route), 2 logic levels.
Constraint Details:
7.635ns physical path delay rst_n to U1_ddr_sdram_mem_top/U1_DQSDLL
1.540ns RST_SET requirement
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.570 AB2.PAD to AB2.PADDI rst_n
ROUTE 666 5.731 AB2.PADDI to R2C20C.C0 rst_n_c
CTOF_DEL --- 0.300 R2C20C.C0 to R2C20C.F0 SLICE_990
ROUTE 1 1.034 R2C20C.F0 to TDLL.RST rst_n_c_iZ0 (to pll_clk)
--------
7.635 (11.4% logic, 88.6% route), 2 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "pll_clk" 167.000000 MHz | | |
; | 167.001 MHz| 170.184 MHz| 8
| | |
FREQUENCY NET "clk_in_c" 40.000000 MHz | | |
; | 40.000 MHz| 251.383 MHz| 4
| | |
BLOCK PATH FROM PORT "rst_n" ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Timing summary:
Timing errors: 0 Score: 0
Constraints cover 5681 paths, 4 nets, and 5652 connections (84.3% coverage)
--------------------------------------------------------------------------------
Generated from the file 'C:\EVALUATION BOARDS\XP\HIGH_END\EVAL_CODE\DDR\VHDL\PNR\ddr_vhdl_pnr.twr'