PAD Specification File *************************** PART TYPE: LFXP10C SPEED GRADE: 5 PACKAGE: FPBGA388 Package: Version 1.13.1.2, Status: PRODUCTION Thu Jun 23 11:12:25 2005 Pinout by Port Name: +-----------------------------------------+--------------------+--------------------+--------------------------+ | Port Name | Pin/Bank | Buffer Type | Properties | +-----------------------------------------+--------------------+--------------------+--------------------------+ | VREF1_BANK_2 | L21/2 | | VREF1_DRIVER | | clk_in | A10/0 | LVCMOS25_IN | SLEW:FAST | | ddr_addr_0 | R19/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_1 | R21/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_10 | T22/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_11 | M19/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_12 | M22/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_2 | P19/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_3 | R22/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_4 | P22/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_5 | P20/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_6 | N19/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_7 | P21/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_8 | M20/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_addr_9 | N21/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_ba_0 | V22/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_ba_1 | T19/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_cas_n | T20/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_cke0 | J20/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_cke1 | J19/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_clk | H19/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_clk_n | G19/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_cs_n1 | U20/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_cs_n_0 | W22/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_0 | F21/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_1 | E22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_10 | K22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_11 | L22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_12 | J21/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_13 | K19/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_14 | L19/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_15 | L20/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_16 | Y1/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_17 | W2/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_18 | AB11/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_19 | AA11/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_2 | F22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_20 | R2/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_21 | T1/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_22 | V1/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_23 | U2/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_24 | W15/4 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_25 | W14/4 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_26 | Y11/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_27 | Y12/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_28 | P4/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_29 | P3/6 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_3 | G22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_30 | AB9/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_31 | AA9/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_data_4 | D21/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_5 | E21/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_6 | F20/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_7 | H20/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_8 | H22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_data_9 | J22/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_dm_0 | D22/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_dm_1 | K21/2 | SSTL25_II_OUT | SLEW:FAST | | ddr_dm_2 | Y10/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_dm_3 | AA7/5 | SSTL25_II_OUT | SLEW:FAST | | ddr_dqs_0 | G21/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_dqs_1 | K20/2 | SSTL25_II_BIDI | SLEW:FAST VREF1_LOAD | | ddr_dqs_2 | C21/1 | SSTL25_II_OUT | SLEW:FAST | | ddr_dqs_3 | C22/1 | SSTL25_II_OUT | SLEW:FAST | | ddr_ras_n | U19/3 | SSTL25_II_OUT | SLEW:FAST | | ddr_we_n | U21/3 | SSTL25_II_OUT | SLEW:FAST | | debug_port_a_0 | B13/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_1 | B12/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_10 | C3/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_11 | B4/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_12 | B3/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_13 | A4/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_14 | A3/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_15 | A2/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_2 | A18/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_3 | A13/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_4 | A12/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_5 | D9/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_6 | D8/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_7 | D3/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_8 | C5/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_a_9 | C4/0 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_0 | K4/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_1 | J4/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_10 | E2/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_11 | E1/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_12 | D2/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_13 | D1/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_14 | D12/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_15 | B22/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_2 | H4/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_3 | G3/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_4 | G2/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_5 | G1/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_6 | F3/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_7 | F2/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_8 | F1/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | debug_port_b_9 | E3/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST PULL:UP | ledout_0 | H1/7 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_1 | B16/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_2 | B18/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_3 | C18/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_4 | C19/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_5 | C20/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_6 | W16/4 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | ledout_7 | A16/1 | LVCMOS25_OUT | DRIVE:12mA SLEW:FAST | | rst_n | AB2/5 | LVCMOS25_IN | SLEW:FAST PULL:UP | | vref1A | A8/0 | LVCMOS25_IN | SLEW:FAST | | vref1B | A17/1 | LVCMOS25_IN | SLEW:FAST | | vref1D | B21/1 | LVCMOS25_IN | SLEW:FAST | | vref2A | A6/0 | LVCMOS25_IN | SLEW:FAST | | vref2B | R20/3 | LVCMOS25_IN | SLEW:FAST | | vref2C | G20/2 | LVCMOS25_IN | SLEW:FAST | | vref2D | N20/3 | LVCMOS25_IN | SLEW:FAST | +-----------------------------------------+--------------------+--------------------+--------------------------+ Vccio by Bank: +--------------------+--------------------+ | Bank | Vccio | +--------------------+--------------------+ | 0 | 2.5V | | 1 | 2.5V | | 2 | 2.5V | | 3 | 2.5V | | 4 | 2.5V | | 5 | 2.5V | | 6 | 2.5V | | 7 | 2.5V | +--------------------+--------------------+ Vref by Bank: +--------------------+---------+--------------------+-------------------------------+ | Vref | Pin | Bank # / Vref # | Load | +--------------------+---------+--------------------+-------------------------------+ | VREF1_BANK_2 | L21 | 2 / VREF1 (1.25V) | L22 K22 L19 K20 L20 | | | | | J22 J21 H22 K19 H20 | | | | | G22 G21 F20 F22 F21 | | | | | E22 E21 D21 | +--------------------+---------+--------------------+-------------------------------+ Pinout by Pin Number: +--------------------+--------------------+--------------------+--------------------+ | Pin/Bank | Pin Info | Preference | Buffer Type | +--------------------+--------------------+--------------------+--------------------+ | A2/0 | debug_port_a_15 | | LVCMOS25_OUT | | A3/0 | debug_port_a_14 | | LVCMOS25_OUT | | A4/0 | debug_port_a_13 | | LVCMOS25_OUT | | A5/0 | | | | | A6/0 | vref2A | | LVCMOS25_IN | | A7/0 | | | | | A8/0 | vref1A | | LVCMOS25_IN | | A9/0 | | | | | A10/0 | clk_in | | LVCMOS25_IN | | A11/0 | | | | | A12/1 | debug_port_a_4 | | LVCMOS25_OUT | | A13/1 | debug_port_a_3 | | LVCMOS25_OUT | | A14/1 | | | | | A15/1 | | | | | A16/1 | ledout_7 | | LVCMOS25_OUT | | A17/1 | vref1B | | LVCMOS25_IN | | A18/1 | debug_port_a_2 | | LVCMOS25_OUT | | A19/1 | | | | | A20/1 | | | | | A21/1 | | | | | AA3/5 | | | | | AA4/5 | | | | | AA5/5 | | | | | AA6/5 | | | | | AA7/5 | ddr_dm_3 | | SSTL25_II_OUT | | AA8/5 | | | | | AA9/5 | ddr_data_31 | | SSTL25_II_OUT | | AA10/5 | | | | | AA11/5 | ddr_data_19 | | SSTL25_II_OUT | | AA12/4 | | | | | AA13/4 | | | | | AA14/4 | | | | | AA15/4 | | | | | AA16/4 | | | | | AA17/4 | | | | | AA18/4 | | | | | AA19/4 | | | | | AA20/4 | | | | | AA21/4 | | | | | AA22/4 | | | | | AB2/5 | rst_n | | LVCMOS25_IN | | AB3/5 | | | | | AB4/5 | | | | | AB5/5 | | | | | AB6/5 | | | | | AB7/5 | | | | | AB8/5 | | | | | AB9/5 | ddr_data_30 | | SSTL25_II_OUT | | AB10/5 | | | | | AB11/5 | ddr_data_18 | | SSTL25_II_OUT | | AB12/4 | | | | | AB13/4 | | | | | AB14/4 | | | | | AB15/4 | | | | | AB16/4 | | | | | AB17/4 | | | | | AB18/4 | | | | | AB19/4 | | | | | AB20/4 | | | | | AB21/4 | | | | | B3/0 | debug_port_a_12 | | LVCMOS25_OUT | | B4/0 | debug_port_a_11 | | LVCMOS25_OUT | | B5/0 | | | | | B6/0 | | | | | B7/0 | | | | | B8/0 | | | | | B9/0 | | | | | B10/0 | | | | | B11/0 | | | | | B12/1 | debug_port_a_1 | | LVCMOS25_OUT | | B13/1 | debug_port_a_0 | | LVCMOS25_OUT | | B14/1 | | | | | B15/1 | | | | | B16/1 | ledout_1 | | LVCMOS25_OUT | | B17/1 | | | | | B18/1 | ledout_2 | | LVCMOS25_OUT | | B19/1 | | | | | B20/1 | | | | | B21/1 | vref1D | | LVCMOS25_IN | | B22/1 | debug_port_b_15 | | LVCMOS25_OUT | | C3/0 | debug_port_a_10 | | LVCMOS25_OUT | | C4/0 | debug_port_a_9 | | LVCMOS25_OUT | | C5/0 | debug_port_a_8 | | LVCMOS25_OUT | | C6/0 | | | | | C7/0 | | | | | C8/0 | | | | | C9/0 | | | | | C10/0 | | | | | C11/0 | | | | | C12/1 | | | | | C13/1 | | | | | C14/1 | | | | | C18/1 | ledout_3 | | LVCMOS25_OUT | | C19/1 | ledout_4 | | LVCMOS25_OUT | | C20/1 | ledout_5 | | LVCMOS25_OUT | | C21/1 | ddr_dqs_2 | | SSTL25_II_OUT | | C22/1 | ddr_dqs_3 | | SSTL25_II_OUT | | D1/7 | debug_port_b_13 | | LVCMOS25_OUT | | D2/7 | debug_port_b_12 | | LVCMOS25_OUT | | D3/0 | debug_port_a_7 | | LVCMOS25_OUT | | D8/0 | debug_port_a_6 | | LVCMOS25_OUT | | D9/0 | debug_port_a_5 | | LVCMOS25_OUT | | D10/0 | | | | | D11/0 | | | | | D12/1 | debug_port_b_14 | | LVCMOS25_OUT | | D13/1 | | | | | D14/1 | | | | | D15/1 | | | | | D21/2 | ddr_data_4 | | SSTL25_II_BIDI | | D22/2 | ddr_dm_0 | | SSTL25_II_OUT | | E1/7 | debug_port_b_11 | | LVCMOS25_OUT | | E2/7 | debug_port_b_10 | | LVCMOS25_OUT | | E3/7 | debug_port_b_9 | | LVCMOS25_OUT | | E21/2 | ddr_data_5 | | SSTL25_II_BIDI | | E22/2 | ddr_data_1 | | SSTL25_II_BIDI | | F1/7 | debug_port_b_8 | | LVCMOS25_OUT | | F2/7 | debug_port_b_7 | | LVCMOS25_OUT | | F3/7 | debug_port_b_6 | | LVCMOS25_OUT | | F20/2 | ddr_data_6 | | SSTL25_II_BIDI | | F21/2 | ddr_data_0 | | SSTL25_II_BIDI | | F22/2 | ddr_data_2 | | SSTL25_II_BIDI | | G1/7 | debug_port_b_5 | | LVCMOS25_OUT | | G2/7 | debug_port_b_4 | | LVCMOS25_OUT | | G3/7 | debug_port_b_3 | | LVCMOS25_OUT | | G19/2 | ddr_clk_n | | SSTL25_II_OUT | | G20/2 | vref2C | | LVCMOS25_IN | | G21/2 | ddr_dqs_0 | | SSTL25_II_BIDI | | G22/2 | ddr_data_3 | | SSTL25_II_BIDI | | H1/7 | ledout_0 | | LVCMOS25_OUT | | H2/7 | | | | | H3/7 | | | | | H4/7 | debug_port_b_2 | | LVCMOS25_OUT | | H19/2 | ddr_clk | | SSTL25_II_OUT | | H20/2 | ddr_data_7 | | SSTL25_II_BIDI | | H21/2 | | | | | H22/2 | ddr_data_8 | | SSTL25_II_BIDI | | J1/7 | | | | | J2/7 | | | | | J3/7 | | | | | J4/7 | debug_port_b_1 | | LVCMOS25_OUT | | J19/2 | ddr_cke1 | | SSTL25_II_OUT | | J20/2 | ddr_cke0 | | SSTL25_II_OUT | | J21/2 | ddr_data_12 | | SSTL25_II_BIDI | | J22/2 | ddr_data_9 | | SSTL25_II_BIDI | | K1/7 | | | | | K2/7 | | | | | K3/7 | | | | | K4/7 | debug_port_b_0 | | LVCMOS25_OUT | | K19/2 | ddr_data_13 | | SSTL25_II_BIDI | | K20/2 | ddr_dqs_1 | | SSTL25_II_BIDI | | K21/2 | ddr_dm_1 | | SSTL25_II_OUT | | K22/2 | ddr_data_10 | | SSTL25_II_BIDI | | L1/7 | | | | | L2/7 | | | | | L3/7 | | | | | L4/7 | | | | | L19/2 | ddr_data_14 | | SSTL25_II_BIDI | | L20/2 | ddr_data_15 | | SSTL25_II_BIDI | | L21/2 | VREF1_BANK_2 | | | | L22/2 | ddr_data_11 | | SSTL25_II_BIDI | | M1/7 | | | | | M3/6 | | | | | M4/6 | | | | | M19/3 | ddr_addr_11 | | SSTL25_II_OUT | | M20/3 | ddr_addr_8 | | SSTL25_II_OUT | | M22/2 | ddr_addr_12 | | SSTL25_II_OUT | | N2/6 | | | | | N3/6 | | | | | N4/6 | | | | | N19/3 | ddr_addr_6 | | SSTL25_II_OUT | | N20/3 | vref2D | | LVCMOS25_IN | | N21/3 | ddr_addr_9 | | SSTL25_II_OUT | | P1/6 | | | | | P2/6 | | | | | P3/6 | ddr_data_29 | | SSTL25_II_OUT | | P4/6 | ddr_data_28 | | SSTL25_II_OUT | | P19/3 | ddr_addr_2 | | SSTL25_II_OUT | | P20/3 | ddr_addr_5 | | SSTL25_II_OUT | | P21/3 | ddr_addr_7 | | SSTL25_II_OUT | | P22/3 | ddr_addr_4 | | SSTL25_II_OUT | | PB2B/0 | | | | | PB8B/0 | | | | | PB9A/0 | | | | | PB16B/0 | | | | | PB17A/0 | | | | | PB24B/0 | | | | | PB25A/0 | | | | | PB32B/0 | | | | | PB33A/0 | | | | | PB39B/0 | | | | | PL5B/0 | | | | | PL6A/0 | | | | | PL14B/0 | | | | | PL15A/0 | | | | | PL22B/0 | | | | | PL23A/0 | | | | | PL31B/0 | | | | | PL32A/0 | | | | | PR5B/0 | | | | | PR6A/0 | | | | | PR14B/0 | | | | | PR15A/0 | | | | | PR22B/0 | | | | | PR23A/0 | | | | | PR31B/0 | | | | | PR32A/0 | | | | | PT2B/0 | | | | | PT8B/0 | | | | | PT9A/0 | | | | | PT16B/0 | | | | | PT17A/0 | | | | | PT24B/0 | | | | | PT25A/0 | | | | | PT32B/0 | | | | | PT33A/0 | | | | | PT39B/0 | | | | | R1/6 | | | | | R2/6 | ddr_data_20 | | SSTL25_II_OUT | | R3/6 | | | | | R4/6 | | | | | R19/3 | ddr_addr_0 | | SSTL25_II_OUT | | R20/3 | vref2B | | LVCMOS25_IN | | R21/3 | ddr_addr_1 | | SSTL25_II_OUT | | R22/3 | ddr_addr_3 | | SSTL25_II_OUT | | T1/6 | ddr_data_21 | | SSTL25_II_OUT | | T2/6 | | | | | T3/6 | | | | | T4/6 | | | | | T19/3 | ddr_ba_1 | | SSTL25_II_OUT | | T20/3 | ddr_cas_n | | SSTL25_II_OUT | | T21/3 | | | | | T22/3 | ddr_addr_10 | | SSTL25_II_OUT | | TCK/1 | | | | | TDI/1 | | | | | TDO/2 | | | | | TMS/1 | | | | | U1/6 | | | | | U2/6 | ddr_data_23 | | SSTL25_II_OUT | | U3/6 | | | | | U4/6 | | | | | U19/3 | ddr_ras_n | | SSTL25_II_OUT | | U20/3 | ddr_cs_n1 | | SSTL25_II_OUT | | U21/3 | ddr_we_n | | SSTL25_II_OUT | | U22/3 | | | | | V1/6 | ddr_data_22 | | SSTL25_II_OUT | | V2/6 | | | | | V3/6 | | | | | V4/6 | | | | | V19/3 | | | | | V20/3 | | | | | V21/3 | | | | | V22/3 | ddr_ba_0 | | SSTL25_II_OUT | | W1/6 | | | | | W2/6 | ddr_data_17 | | SSTL25_II_OUT | | W6/5 | | | | | W8/5 | | | | | W9/5 | | | | | W10/5 | | | | | W11/5 | | | | | W12/4 | | | | | W13/4 | | | | | W14/4 | ddr_data_25 | | SSTL25_II_OUT | | W15/4 | ddr_data_24 | | SSTL25_II_OUT | | W16/4 | ledout_6 | | LVCMOS25_OUT | | W21/3 | | | | | W22/3 | ddr_cs_n_0 | | SSTL25_II_OUT | | Y1/6 | ddr_data_16 | | SSTL25_II_OUT | | Y4/5 | | | | | Y5/5 | | | | | Y6/5 | | | | | Y7/5 | | | | | Y8/5 | | | | | Y9/5 | | | | | Y10/5 | ddr_dm_2 | | SSTL25_II_OUT | | Y11/5 | ddr_data_26 | | SSTL25_II_OUT | | Y12/5 | ddr_data_27 | | SSTL25_II_OUT | | Y13/4 | | | | | Y14/4 | | | | | Y17/4 | | | | | Y18/4 | | | | | Y19/4 | | | | | Y20/4 | | | | | Y21/4 | | | | | Y22/3 | | | | +--------------------+--------------------+--------------------+--------------------+ Locate Preferences for each Pin: LOCATE COMP "clk_in" SITE "A10"; LOCATE COMP "ddr_addr_0" SITE "R19"; LOCATE COMP "ddr_addr_1" SITE "R21"; LOCATE COMP "ddr_addr_10" SITE "T22"; LOCATE COMP "ddr_addr_11" SITE "M19"; LOCATE COMP "ddr_addr_12" SITE "M22"; LOCATE COMP "ddr_addr_2" SITE "P19"; LOCATE COMP "ddr_addr_3" SITE "R22"; LOCATE COMP "ddr_addr_4" SITE "P22"; LOCATE COMP "ddr_addr_5" SITE "P20"; LOCATE COMP "ddr_addr_6" SITE "N19"; LOCATE COMP "ddr_addr_7" SITE "P21"; LOCATE COMP "ddr_addr_8" SITE "M20"; LOCATE COMP "ddr_addr_9" SITE "N21"; LOCATE COMP "ddr_ba_0" SITE "V22"; LOCATE COMP "ddr_ba_1" SITE "T19"; LOCATE COMP "ddr_cas_n" SITE "T20"; LOCATE COMP "ddr_cke0" SITE "J20"; LOCATE COMP "ddr_cke1" SITE "J19"; LOCATE COMP "ddr_clk" SITE "H19"; LOCATE COMP "ddr_clk_n" SITE "G19"; LOCATE COMP "ddr_cs_n1" SITE "U20"; LOCATE COMP "ddr_cs_n_0" SITE "W22"; LOCATE COMP "ddr_data_0" SITE "F21"; LOCATE COMP "ddr_data_1" SITE "E22"; LOCATE COMP "ddr_data_10" SITE "K22"; LOCATE COMP "ddr_data_11" SITE "L22"; LOCATE COMP "ddr_data_12" SITE "J21"; LOCATE COMP "ddr_data_13" SITE "K19"; LOCATE COMP "ddr_data_14" SITE "L19"; LOCATE COMP "ddr_data_15" SITE "L20"; LOCATE COMP "ddr_data_16" SITE "Y1"; LOCATE COMP "ddr_data_17" SITE "W2"; LOCATE COMP "ddr_data_18" SITE "AB11"; LOCATE COMP "ddr_data_19" SITE "AA11"; LOCATE COMP "ddr_data_2" SITE "F22"; LOCATE COMP "ddr_data_20" SITE "R2"; LOCATE COMP "ddr_data_21" SITE "T1"; LOCATE COMP "ddr_data_22" SITE "V1"; LOCATE COMP "ddr_data_23" SITE "U2"; LOCATE COMP "ddr_data_24" SITE "W15"; LOCATE COMP "ddr_data_25" SITE "W14"; LOCATE COMP "ddr_data_26" SITE "Y11"; LOCATE COMP "ddr_data_27" SITE "Y12"; LOCATE COMP "ddr_data_28" SITE "P4"; LOCATE COMP "ddr_data_29" SITE "P3"; LOCATE COMP "ddr_data_3" SITE "G22"; LOCATE COMP "ddr_data_30" SITE "AB9"; LOCATE COMP "ddr_data_31" SITE "AA9"; LOCATE COMP "ddr_data_4" SITE "D21"; LOCATE COMP "ddr_data_5" SITE "E21"; LOCATE COMP "ddr_data_6" SITE "F20"; LOCATE COMP "ddr_data_7" SITE "H20"; LOCATE COMP "ddr_data_8" SITE "H22"; LOCATE COMP "ddr_data_9" SITE "J22"; LOCATE COMP "ddr_dm_0" SITE "D22"; LOCATE COMP "ddr_dm_1" SITE "K21"; LOCATE COMP "ddr_dm_2" SITE "Y10"; LOCATE COMP "ddr_dm_3" SITE "AA7"; LOCATE COMP "ddr_dqs_0" SITE "G21"; LOCATE COMP "ddr_dqs_1" SITE "K20"; LOCATE COMP "ddr_dqs_2" SITE "C21"; LOCATE COMP "ddr_dqs_3" SITE "C22"; LOCATE COMP "ddr_ras_n" SITE "U19"; LOCATE COMP "ddr_we_n" SITE "U21"; LOCATE COMP "debug_port_a_0" SITE "B13"; LOCATE COMP "debug_port_a_1" SITE "B12"; LOCATE COMP "debug_port_a_10" SITE "C3"; LOCATE COMP "debug_port_a_11" SITE "B4"; LOCATE COMP "debug_port_a_12" SITE "B3"; LOCATE COMP "debug_port_a_13" SITE "A4"; LOCATE COMP "debug_port_a_14" SITE "A3"; LOCATE COMP "debug_port_a_15" SITE "A2"; LOCATE COMP "debug_port_a_2" SITE "A18"; LOCATE COMP "debug_port_a_3" SITE "A13"; LOCATE COMP "debug_port_a_4" SITE "A12"; LOCATE COMP "debug_port_a_5" SITE "D9"; LOCATE COMP "debug_port_a_6" SITE "D8"; LOCATE COMP "debug_port_a_7" SITE "D3"; LOCATE COMP "debug_port_a_8" SITE "C5"; LOCATE COMP "debug_port_a_9" SITE "C4"; LOCATE COMP "debug_port_b_0" SITE "K4"; LOCATE COMP "debug_port_b_1" SITE "J4"; LOCATE COMP "debug_port_b_10" SITE "E2"; LOCATE COMP "debug_port_b_11" SITE "E1"; LOCATE COMP "debug_port_b_12" SITE "D2"; LOCATE COMP "debug_port_b_13" SITE "D1"; LOCATE COMP "debug_port_b_14" SITE "D12"; LOCATE COMP "debug_port_b_15" SITE "B22"; LOCATE COMP "debug_port_b_2" SITE "H4"; LOCATE COMP "debug_port_b_3" SITE "G3"; LOCATE COMP "debug_port_b_4" SITE "G2"; LOCATE COMP "debug_port_b_5" SITE "G1"; LOCATE COMP "debug_port_b_6" SITE "F3"; LOCATE COMP "debug_port_b_7" SITE "F2"; LOCATE COMP "debug_port_b_8" SITE "F1"; LOCATE COMP "debug_port_b_9" SITE "E3"; LOCATE COMP "ledout_0" SITE "H1"; LOCATE COMP "ledout_1" SITE "B16"; LOCATE COMP "ledout_2" SITE "B18"; LOCATE COMP "ledout_3" SITE "C18"; LOCATE COMP "ledout_4" SITE "C19"; LOCATE COMP "ledout_5" SITE "C20"; LOCATE COMP "ledout_6" SITE "W16"; LOCATE COMP "ledout_7" SITE "A16"; LOCATE COMP "rst_n" SITE "AB2"; LOCATE COMP "vref1A" SITE "A8"; LOCATE COMP "vref1B" SITE "A17"; LOCATE COMP "vref1D" SITE "B21"; LOCATE COMP "vref2A" SITE "A6"; LOCATE COMP "vref2B" SITE "R20"; LOCATE COMP "vref2C" SITE "G20"; LOCATE COMP "vref2D" SITE "N20"; #PLL LOCATE COMP "U1_ddr_sdram_mem_top/U1_kbar_clk_pll/I1" SITE "PLL3_R27C1" ; #DQSDLL LOCATE COMP "U1_ddr_sdram_mem_top/U1_DQSDLL" SITE "TDLL" ; LOCATE VREF "VREF1_BANK_2" SITE "L21" LEVELMODE "SSTL25_II_BIDI"; PAR: Place And Route ispLever_v50_Production_Build (40). Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved. Thu Jun 23 11:12:25 2005 Generated from the file 'C:\EVALUATION BOARDS\XP\HIGH_END\EVAL_CODE\DDR\VERILOG\PNR\ddr_verilog_pnr.pad'