--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v50_SP1_Build (17)
Wed Jun 29 15:05:02 2005
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr fcram_verilog_pnr.ncd fcram_verilog_pnr.prf
Design file: fcram_verilog_pnr.ncd
Preference file: fcram_verilog_pnr.prf
Device,speed: LFEC20E,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "pll_clk" 167.000000 MHz (5 errors)
4096 items scored, 5 timing errors detected.
Warning: 163.159MHz is the maximum frequency for this preference.
FREQUENCY NET "clk_in_c" 40.000000 MHz (0 errors)
214 items scored, 0 timing errors detected.
Report: 235.627MHz is the maximum frequency for this preference.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/datavalid_inv" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" TO CELL "U1_fcram_top/ddr_io_u/data_validZ0Z_*" 10.000000 ns (0 errors)
1 item scored, 0 timing errors detected.
MAXDELAY NET "data_valid_*" 4.000000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "din0_*" 4.000000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "din1_*" 4.000000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout0_d3Z0Z_*" 4.400000 nS (0 errors)
8 items scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout1_d3Z0Z_*" 4.400000 nS (0 errors)
8 items scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_i" 4.400000 nS (0 errors)
1 item scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_dZ0Z_*" 4.400000 nS (0 errors)
3 items scored, 0 timing errors detected.
MAXDELAY NET "din0_*" 4.400000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "din1_*" 4.400000 nS (0 errors)
0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_dqs_*" MAX 7.250000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_pdn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_csn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_fn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_addr_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
15 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_ba_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
2 items scored, 0 timing errors detected.
================================================================================
Preference: FREQUENCY NET "pll_clk" 167.000000 MHz ;
4096 items scored, 5 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 0.141ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fcram_app_drv_u/usr_addri_int_ff_25 (from pll_clk +)
Destination: FF Data in U1_fcram_top/fcram_core_u/fcram_sm_u/ba_int_0 (to pll_clk +)
Delay: 6.012ns (30.3% logic, 69.7% route), 6 logic levels.
Constraint Details:
6.012ns physical path delay SLICE_288 to SLICE_164 exceeds
5.988ns delay constraint less
0.000ns skew and
0.117ns DIN_SET requirement (totaling 5.871ns) by 0.141ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.363 R13C25B.CLK to R13C25B.Q0 SLICE_288 (from pll_clk)
ROUTE 5 1.238 R13C25B.Q0 to R13C30C.M0 U1_fcram_top/usr_addri_int_25
MTOOFX_DEL --- 0.325 R13C30C.M0 to R13C30C.OFX0 SLICE_374
ROUTE 14 1.329 R13C30C.OFX0 to R12C27C.A0 U1_fcram_top/fcram_core_u/fcram_sm_u/N_1757
CTOF_DEL --- 0.241 R12C27C.A0 to R12C27C.F0 SLICE_484
ROUTE 2 0.465 R12C27C.F0 to R12C28B.D0 U1_fcram_top/fcram_core_u/fcram_sm_u/N_1447
CTOOFX_DEL --- 0.409 R12C28B.D0 to R12C28B.OFX0 SLICE_209
ROUTE 7 0.606 R12C28B.OFX0 to R12C29C.C1 U1_fcram_top/fcram_core_u/fcram_sm_u/ld_usr_addr_9_0_0_n
CTOF_DEL --- 0.241 R12C29C.C1 to R12C29C.F1 SLICE_485
ROUTE 1 0.554 R12C29C.F1 to R11C29D.C0 U1_fcram_top/fcram_core_u/fcram_sm_u/ba_int_20_iv_1_s_n_0
CTOF_DEL --- 0.241 R11C29D.C0 to R11C29D.F0 SLICE_164
ROUTE 1 0.000 R11C29D.F0 to R11C29D.DI0 U1_fcram_top/fcram_core_u/fcram_sm_u/ba_int_20_iv_1_n_0 (to pll_clk)
--------
6.012 (30.3% logic, 69.7% route), 6 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
2.911ns PLL3_R40C1.CLKOP to R13C25B.CLK
Destination Clock:
Delay Connection
2.911ns PLL3_R40C1.CLKOP to R11C29D.CLK
Warning: 163.159MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk_in_c" 40.000000 MHz ;
214 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 20.756ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q wait_200us_count1_0_F1 (from E5GDCS21_clk_in_c +)
Destination: FF Data in waited_200us (to E5GDCS21_clk_in_c +)
Delay: 4.127ns (26.3% logic, 73.7% route), 4 logic levels.
Constraint Details:
4.127ns physical path delay SLICE_60 to SLICE_360 meets
25.000ns delay constraint less
0.000ns skew and
0.117ns DIN_SET requirement (totaling 24.883ns) by 20.756ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.363 R38C2A.CLK to R38C2A.Q0 SLICE_60 (from E5GDCS21_clk_in_c)
ROUTE 2 1.330 R38C2A.Q0 to R37C2D.C0 wait_200us_count_0
CTOF_DEL --- 0.241 R37C2D.C0 to R37C2D.F0 SLICE_509
ROUTE 1 0.744 R37C2D.F0 to R37C3A.B1 G_2Z0Z_12
CTOF_DEL --- 0.241 R37C3A.B1 to R37C3A.F1 SLICE_411
ROUTE 1 0.967 R37C3A.F1 to R37C4B.B0 G_2Z0Z_21
CTOF_DEL --- 0.241 R37C4B.B0 to R37C4B.F0 SLICE_360
ROUTE 1 0.000 R37C4B.F0 to R37C4B.DI0 GZ0Z_1 (to E5GDCS21_clk_in_c)
--------
4.127 (26.3% logic, 73.7% route), 4 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
0.447ns LLDCS1.DCSOUT to R38C2A.CLK
Destination Clock :
Delay Connection
0.447ns LLDCS1.DCSOUT to R37C4B.CLK
Report: 235.627MHz is the maximum frequency for this preference.
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/datavalid_inv" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" TO CELL "U1_fcram_top/ddr_io_u/data_validZ0Z_*" 10.000000 ns ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.021ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0 (from U1_fcram_top/sys_clk_0 -)
Destination: FF Data in U1_fcram_top/ddr_io_u/data_validZ0Z_0 (to pll_clk +)
Delay: 1.372ns (28.9% logic, 71.1% route), 1 logic levels.
Constraint Details:
1.372ns physical path delay SLICE_78 to SLICE_77 meets
10.000ns delay constraint less
4.491ns skew and
0.000ns feedback compensation and
0.116ns M_SET requirement (totaling 5.393ns) by 4.021ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.397 R4C32C.CLK to R4C32C.Q0 SLICE_78 (from U1_fcram_top/sys_clk_0)
ROUTE 1 0.975 R4C32C.Q0 to R4C34A.M0 U1_fcram_top/ddr_io_u/pio_data_valid_0 (to pll_clk)
--------
1.372 (28.9% logic, 71.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.556 F6.PAD to F6.PADDI clk_in
ROUTE 1 5.203 F6.PADDI to LLDCS1.CLK0 clk_in_c
MUX_DEL --- 0.308 LLDCS1.CLK0 to LLDCS1.DCSOUT E5GDCS21
ROUTE 19 0.319 LLDCS1.DCSOUT to LL3_R40C1.CLKI E5GDCS21_clk_in_c
CLK2P_DEL --- 4.491 LL3_R40C1.CLKI to L3_R40C1.CLKOS U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 29 2.911 L3_R40C1.CLKOS to R4C32C.CLK U1_fcram_top/sys_clk_0
--------
13.788 (38.8% logic, 61.2% route), 3 logic levels.
PLL3_R40C1.CLKOS attributes: PHASEADJ = 270, FDEL = 0
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.556 F6.PAD to F6.PADDI clk_in
ROUTE 1 5.203 F6.PADDI to LLDCS1.CLK0 clk_in_c
MUX_DEL --- 0.308 LLDCS1.CLK0 to LLDCS1.DCSOUT E5GDCS21
ROUTE 19 0.319 LLDCS1.DCSOUT to LL3_R40C1.CLKI E5GDCS21_clk_in_c
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.911 L3_R40C1.CLKOP to R4C34A.CLK pll_clk
--------
9.297 (9.3% logic, 90.7% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
================================================================================
Preference: MAXDELAY NET "data_valid_*" 4.000000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "din0_*" 4.000000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "din1_*" 4.000000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout0_d3Z0Z_*" 4.400000 nS ;
8 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 0.995ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout0_d3Z0Z_2 meets
4.400ns delay constraint by 3.405ns
Delays Connection(s)
0.995ns R4C31A.Q0 to R3C31B.M0
Report: 0.995ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout1_d3Z0Z_*" 4.400000 nS ;
8 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 1.495ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout1_d3Z0Z_7 meets
4.400ns delay constraint by 2.905ns
Delays Connection(s)
1.495ns R4C28A.Q1 to R4C29A.M1
Report: 1.495ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_i" 4.400000 nS ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 0.000ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_i meets
4.400ns delay constraint by 4.400ns
Delays Connection(s)
0.000ns R3C30B.F0 to R3C30B.DI0
Report: 0.000ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_dZ0Z_*" 4.400000 nS ;
3 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 1.713ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_dZ0Z_0 meets
4.400ns delay constraint by 2.687ns
Delays Connection(s)
1.675ns R12C30B.Q0 to R3C28A.M0
1.222ns R12C30B.Q0 to R3C30A.C0
1.453ns R12C30B.Q0 to R4C27C.CE
1.453ns R12C30B.Q0 to R4C26C.CE
1.453ns R12C30B.Q0 to R4C27B.CE
1.556ns R12C30B.Q0 to R12C32B.CE
1.713ns R12C30B.Q0 to R3C27A.CE
0.909ns R12C30B.Q0 to R6C28D.CE
1.139ns R12C30B.Q0 to R4C31B.CE
1.399ns R12C30B.Q0 to R5C31A.CE
Report: 1.713ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "din0_*" 4.400000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "din1_*" 4.400000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_dqs_*" MAX 7.250000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.250ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/ddr_io_u/oddrxb_ddr_dqs0 (from pll_clk +)
Destination: Port Pad fcram_dqs_0
Data Path Delay: 3.284ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.783ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.783ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_dqs_0_MGIOL less
2.783ns feedback compensation
3.284ns delay fcram_dqs_0_MGIOL to fcram_dqs_0 less
3.284ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling 0.000ns) meets
7.250ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_dqs_0 by 7.250ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_dqs_0_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T30A.CLK pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Data path fcram_dqs_0_MGIOL to fcram_dqs_0:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 1.455 IOL_T30A.CLK to IOL_T30A.IOLDO fcram_dqs_0_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T30A.IOLDO to F12.IOLDO U1_fcram_top/ddr_io_u/ddr_dqs_buf_out_0
DOPAD_DEL --- 1.829 F12.IOLDO to F12.PAD fcram_dqs_0
--------
3.284 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T9A.CLK pll_clk
C2OUT_DEL --- 1.455 IOL_T9A.CLK to IOL_T9A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T9A.IOLDO to A2.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 1.829 A2.IOLDO to A2.PAD fcram_clk
--------
6.067 (54.1% logic, 45.9% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Report: 0.000ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_pdn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.022ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_pdn (from pll_clk -)
Destination: Port Pad fcram_pdn
Data Path Delay: 3.262ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.783ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.783ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_pdn_MGIOL less
2.783ns feedback compensation
3.262ns delay fcram_pdn_MGIOL to fcram_pdn less
3.284ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.022ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_pdn by 5.022ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_pdn_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T30B.CLK pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Data path fcram_pdn_MGIOL to fcram_pdn:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 1.433 IOL_T30B.CLK to IOL_T30B.IOLDO fcram_pdn_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T30B.IOLDO to F13.IOLDO U1_fcram_top/fpga_io_u/pdn_buf
DOPAD_DEL --- 1.829 F13.IOLDO to F13.PAD fcram_pdn
--------
3.262 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T9A.CLK pll_clk
C2OUT_DEL --- 1.455 IOL_T9A.CLK to IOL_T9A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T9A.IOLDO to A2.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 1.829 A2.IOLDO to A2.PAD fcram_clk
--------
6.067 (54.1% logic, 45.9% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Report: -0.022ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_csn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.022ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3BX_ddr_csn (from pll_clk -)
Destination: Port Pad fcram_csn
Data Path Delay: 3.262ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.783ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.783ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_csn_MGIOL less
2.783ns feedback compensation
3.262ns delay fcram_csn_MGIOL to fcram_csn less
3.284ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.022ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_csn by 5.022ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_csn_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T22B.CLK pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Data path fcram_csn_MGIOL to fcram_csn:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 1.433 IOL_T22B.CLK to IOL_T22B.IOLDO fcram_csn_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T22B.IOLDO to D11.IOLDO U1_fcram_top/fpga_io_u/csn_buf
DOPAD_DEL --- 1.829 D11.IOLDO to D11.PAD fcram_csn
--------
3.262 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T9A.CLK pll_clk
C2OUT_DEL --- 1.455 IOL_T9A.CLK to IOL_T9A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T9A.IOLDO to A2.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 1.829 A2.IOLDO to A2.PAD fcram_clk
--------
6.067 (54.1% logic, 45.9% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Report: -0.022ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_fn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.022ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_fn (from pll_clk -)
Destination: Port Pad fcram_fn
Data Path Delay: 3.262ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.783ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.783ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_fn_MGIOL less
2.783ns feedback compensation
3.262ns delay fcram_fn_MGIOL to fcram_fn less
3.284ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.022ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_fn by 5.022ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_fn_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T22A.CLK pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Data path fcram_fn_MGIOL to fcram_fn:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 1.433 IOL_T22A.CLK to IOL_T22A.IOLDO fcram_fn_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T22A.IOLDO to C11.IOLDO U1_fcram_top/fpga_io_u/fn_buf
DOPAD_DEL --- 1.829 C11.IOLDO to C11.PAD fcram_fn
--------
3.262 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T9A.CLK pll_clk
C2OUT_DEL --- 1.455 IOL_T9A.CLK to IOL_T9A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T9A.IOLDO to A2.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 1.829 A2.IOLDO to A2.PAD fcram_clk
--------
6.067 (54.1% logic, 45.9% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Report: -0.022ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_addr_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
15 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.022ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_addr14 (from pll_clk -)
Destination: Port Pad fcram_addr_14
Data Path Delay: 3.262ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.783ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.783ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_addr_14_MGIOL less
2.783ns feedback compensation
3.262ns delay fcram_addr_14_MGIOL to fcram_addr_14 less
3.284ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.022ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_addr_14 by 5.022ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_addr_14_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T28B.CLK pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Data path fcram_addr_14_MGIOL to fcram_addr_14:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 1.433 IOL_T28B.CLK to IOL_T28B.IOLDO fcram_addr_14_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T28B.IOLDO to A11.IOLDO U1_fcram_top/fpga_io_u/addr_buf_14
DOPAD_DEL --- 1.829 A11.IOLDO to A11.PAD fcram_addr_14
--------
3.262 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T9A.CLK pll_clk
C2OUT_DEL --- 1.455 IOL_T9A.CLK to IOL_T9A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T9A.IOLDO to A2.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 1.829 A2.IOLDO to A2.PAD fcram_clk
--------
6.067 (54.1% logic, 45.9% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Report: -0.022ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_ba_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
2 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.022ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_ba1 (from pll_clk -)
Destination: Port Pad fcram_ba_1
Data Path Delay: 3.262ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.783ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.783ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_ba_1_MGIOL less
2.783ns feedback compensation
3.262ns delay fcram_ba_1_MGIOL to fcram_ba_1 less
3.284ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.022ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_ba_1 by 5.022ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_ba_1_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T26B.CLK pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Data path fcram_ba_1_MGIOL to fcram_ba_1:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 1.433 IOL_T26B.CLK to IOL_T26B.IOLDO fcram_ba_1_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T26B.IOLDO to B10.IOLDO U1_fcram_top/fpga_io_u/ba_buf_1
DOPAD_DEL --- 1.829 B10.IOLDO to B10.PAD fcram_ba_1
--------
3.262 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R40C1.CLKI to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from E5GDCS21_clk_in_c)
ROUTE 333 2.783 L3_R40C1.CLKOP to IOL_T9A.CLK pll_clk
C2OUT_DEL --- 1.455 IOL_T9A.CLK to IOL_T9A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T9A.IOLDO to A2.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 1.829 A2.IOLDO to A2.PAD fcram_clk
--------
6.067 (54.1% logic, 45.9% route), 3 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R40C1.CLKFB to L3_R40C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 333 2.783 L3_R40C1.CLKOP to L3_R40C1.CLKFB pll_clk
--------
2.783 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R40C1.CLKOP attributes: FDEL = 0
Report: -0.022ns is the minimum offset for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "pll_clk" 167.000000 MHz | | |
; | 167.001 MHz| 163.159 MHz| 6
| | |
FREQUENCY NET "clk_in_c" 40.000000 MHz | | |
; | 40.000 MHz| 235.627 MHz| 4
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
prmbdet_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ*" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
prmbdet_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ0" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_read_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ*" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_read_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ0" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_read_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
datavalid_inv" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ*" TO CELL | | |
"U1_fcram_top/ddr_io_u/data_validZ0Z_*" | | |
10.000000 ns ; | -| -| 1
| | |
MAXDELAY NET "data_valid_*" 4.000000 nS | | |
; | -| -| 0
| | |
MAXDELAY NET "din0_*" 4.000000 nS ; | -| -| 0
| | |
MAXDELAY NET "din1_*" 4.000000 nS ; | -| -| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut0_d3Z0Z_*" 4.400000 nS ; | 4.400 ns| 0.995 ns| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut1_d3Z0Z_*" 4.400000 nS ; | 4.400 ns| 1.495 ns| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut_val_i" 4.400000 nS ; | 4.400 ns| 0.000 ns| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut_val_dZ0Z_*" 4.400000 nS ; | 4.400 ns| 1.713 ns| 0
| | |
MAXDELAY NET "din0_*" 4.400000 nS ; | -| -| 0
| | |
MAXDELAY NET "din1_*" 4.400000 nS ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "fcram_dqs_*" MAX | | |
7.250000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 7.250 ns| 0.000 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_pdn" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.022 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_csn" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.022 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_fn" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.022 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_addr_*" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.022 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_ba_*" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.022 ns| 2
| | |
----------------------------------------------------------------------------
1 preference not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
U1_fcram_top/fcram_core_u/fcram_sm_u/ba_| | |
int_20_iv_1_n_0 | 1| 3| 60.00%
| | |
U1_fcram_top/fcram_core_u/fcram_sm_u/ba_| | |
int_20_iv_1_s_n_0 | 1| 3| 60.00%
| | |
U1_fcram_top/fcram_core_u/fcram_sm_u/ld_| | |
usr_addr_9_0_0_n | 7| 3| 60.00%
| | |
U1_fcram_top/fcram_core_u/fcram_sm_u/N_1| | |
757 | 14| 3| 60.00%
| | |
U1_fcram_top/usr_addri_int_25 | 5| 2| 40.00%
| | |
U1_fcram_top/fcram_core_u/fcram_sm_u/N_1| | |
786_1 | 3| 1| 20.00%
| | |
U1_fcram_top/fcram_core_u/fcram_sm_u/pre| | |
v_ba_3Z0Z_0 | 13| 1| 20.00%
| | |
U1_fcram_top/din1_1 | 1| 1| 20.00%
| | |
U1_fcram_top/din0_0 | 1| 1| 20.00%
| | |
----------------------------------------------------------------------------
Timing summary:
Timing errors: 5 Score: 283
Constraints cover 4931 paths, 23 nets, and 3292 connections (94.2% coverage)
--------------------------------------------------------------------------------
Generated from the file 'C:\EVALUATION BOARDS\EC\HIGH_END\EVAL_CODE\FCRAM\VERILOG\PNR\fcram_verilog_pnr.twr'