--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v50_SP1_Build (17)
Tue Jun 28 12:51:45 2005
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr fcram_vhdl_pnr.ncd fcram_vhdl_pnr.prf
Design file: fcram_vhdl_pnr.ncd
Preference file: fcram_vhdl_pnr.prf
Device,speed: LFXP10C,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "pll_clk" 140.000000 MHz (0 errors)
3821 items scored, 0 timing errors detected.
Report: 140.924MHz is the maximum frequency for this preference.
FREQUENCY NET "clk_in_c" 40.000000 MHz (0 errors)
214 items scored, 0 timing errors detected.
Report: 218.388MHz is the maximum frequency for this preference.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/datavalid_inv" 10.000000 ns (0 errors)
0 items scored, 0 timing errors detected.
MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" TO CELL "U1_fcram_top/ddr_io_u/data_validZ0Z_*" 10.000000 ns (0 errors)
1 item scored, 0 timing errors detected.
MAXDELAY NET "data_valid_*" 4.000000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "din0_*" 4.000000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "din1_*" 4.000000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout0_d3Z0Z_*" 4.400000 nS (0 errors)
8 items scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout1_d3Z0Z_*" 4.400000 nS (0 errors)
8 items scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_i" 4.400000 nS (0 errors)
1 item scored, 0 timing errors detected.
MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_dZ0Z_*" 4.400000 nS (0 errors)
3 items scored, 0 timing errors detected.
MAXDELAY NET "din0_*" 4.400000 nS (0 errors)
0 items scored, 0 timing errors detected.
MAXDELAY NET "din1_*" 4.400000 nS (0 errors)
0 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_dqs_*" MAX 7.250000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_pdn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_csn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_fn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
1 item scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_addr_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
15 items scored, 0 timing errors detected.
CLOCK_TO_OUT PORT "fcram_ba_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" (0 errors)
2 items scored, 0 timing errors detected.
================================================================================
Preference: FREQUENCY NET "pll_clk" 140.000000 MHz ;
3821 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.046ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/ddr_io_u/fd1s3ax_din1_2 (from U1_fcram_top/sys_clk_0 -)
Destination: FF Data in U1_fcram_top/fcram_core_u/fcram_rx_u/din1_reclock_p90_2 (to pll_clk +)
Delay: 1.559ns (25.9% logic, 74.1% route), 1 logic levels.
Constraint Details:
1.559ns physical path delay SLICE_91 to SLICE_133 meets
7.142ns delay constraint less
5.357ns skew and
0.000ns feedback compensation and
0.180ns M_SET requirement (totaling 1.605ns) by 0.046ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.404 R2C15D.CLK to R2C15D.Q0 SLICE_91 (from U1_fcram_top/sys_clk_0)
ROUTE 1 1.155 R2C15D.Q0 to R6C16D.M0 U1_fcram_top/din1_2 (to pll_clk)
--------
1.559 (25.9% logic, 74.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.570 A10.PAD to A10.PADDI clk_in
ROUTE 2 2.049 A10.PADDI to LLDCS0.CLK0 clk_in_c
MUX_DEL --- 0.320 LLDCS0.CLK0 to LLDCS0.DCSOUT M5GDCS20
ROUTE 1 0.429 LLDCS0.DCSOUT to LL3_R27C1.CLKI M5GDCS20_clk_in_c
CLK2P_DEL --- 5.357 LL3_R27C1.CLKI to L3_R27C1.CLKOS U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 29 2.622 L3_R27C1.CLKOS to R2C15D.CLK U1_fcram_top/sys_clk_0
--------
11.347 (55.1% logic, 44.9% route), 3 logic levels.
PLL3_R27C1.CLKOS attributes: PHASEADJ = 270, FDEL = 0
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.570 A10.PAD to A10.PADDI clk_in
ROUTE 2 2.049 A10.PADDI to LLDCS0.CLK0 clk_in_c
MUX_DEL --- 0.320 LLDCS0.CLK0 to LLDCS0.DCSOUT M5GDCS20
ROUTE 1 0.429 LLDCS0.DCSOUT to LL3_R27C1.CLKI M5GDCS20_clk_in_c
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.622 L3_R27C1.CLKOP to R6C16D.CLK pll_clk
--------
5.990 (14.9% logic, 85.1% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: 140.924MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "clk_in_c" 40.000000 MHz ;
214 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 20.421ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q wait_200us_count1_0_F1 (from M5GDCS00_clk_in_c +)
Destination: FF Data in waited_200us (to M5GDCS00_clk_in_c +)
Delay: 4.450ns (27.9% logic, 72.1% route), 4 logic levels.
Constraint Details:
4.450ns physical path delay SLICE_68 to SLICE_374 meets
25.000ns delay constraint less
0.000ns skew and
0.129ns DIN_SET requirement (totaling 24.871ns) by 20.421ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.342 R13C8A.CLK to R13C8A.Q0 SLICE_68 (from M5GDCS00_clk_in_c)
ROUTE 2 1.668 R13C8A.Q0 to R12C8A.B0 wait_200us_count_0
CTOF_DEL --- 0.300 R12C8A.B0 to R12C8A.F0 SLICE_463
ROUTE 1 1.086 R12C8A.F0 to R12C9D.B1 G_2Z0Z_12
CTOF_DEL --- 0.300 R12C9D.B1 to R12C9D.F1 SLICE_411
ROUTE 1 0.454 R12C9D.F1 to R12C10D.D0 G_2Z0Z_21
CTOF_DEL --- 0.300 R12C10D.D0 to R12C10D.F0 SLICE_374
ROUTE 1 0.000 R12C10D.F0 to R12C10D.DI0 GZ0Z_1 (to M5GDCS00_clk_in_c)
--------
4.450 (27.9% logic, 72.1% route), 4 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
0.460ns ULDCS0.DCSOUT to R13C8A.CLK
Destination Clock :
Delay Connection
0.460ns ULDCS0.DCSOUT to R12C10D.CLK
Report: 218.388MHz is the maximum frequency for this preference.
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/prmbdet_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_read_dZ0" TO CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/datavalid_inv" 10.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MULTICYCLE FROM CELL "U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ*" TO CELL "U1_fcram_top/ddr_io_u/data_validZ0Z_*" 10.000000 ns ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.576ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/pio_data_validZ0 (from U1_fcram_top/sys_clk_0 -)
Destination: FF Data in U1_fcram_top/ddr_io_u/data_validZ0Z_0 (to pll_clk +)
Delay: 1.887ns (21.4% logic, 78.6% route), 1 logic levels.
Constraint Details:
1.887ns physical path delay SLICE_83 to SLICE_82 meets
10.000ns delay constraint less
5.357ns skew and
0.000ns feedback compensation and
0.180ns M_SET requirement (totaling 4.463ns) by 2.576ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.404 R7C18B.CLK to R7C18B.Q0 SLICE_83 (from U1_fcram_top/sys_clk_0)
ROUTE 1 1.483 R7C18B.Q0 to R13C15D.M0 U1_fcram_top/ddr_io_u/pio_data_valid_0 (to pll_clk)
--------
1.887 (21.4% logic, 78.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.570 A10.PAD to A10.PADDI clk_in
ROUTE 2 2.049 A10.PADDI to LLDCS0.CLK0 clk_in_c
MUX_DEL --- 0.320 LLDCS0.CLK0 to LLDCS0.DCSOUT M5GDCS20
ROUTE 1 0.429 LLDCS0.DCSOUT to LL3_R27C1.CLKI M5GDCS20_clk_in_c
CLK2P_DEL --- 5.357 LL3_R27C1.CLKI to L3_R27C1.CLKOS U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 29 2.622 L3_R27C1.CLKOS to R7C18B.CLK U1_fcram_top/sys_clk_0
--------
11.347 (55.1% logic, 44.9% route), 3 logic levels.
PLL3_R27C1.CLKOS attributes: PHASEADJ = 270, FDEL = 0
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.570 A10.PAD to A10.PADDI clk_in
ROUTE 2 2.049 A10.PADDI to LLDCS0.CLK0 clk_in_c
MUX_DEL --- 0.320 LLDCS0.CLK0 to LLDCS0.DCSOUT M5GDCS20
ROUTE 1 0.429 LLDCS0.DCSOUT to LL3_R27C1.CLKI M5GDCS20_clk_in_c
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.622 L3_R27C1.CLKOP to R13C15D.CLK pll_clk
--------
5.990 (14.9% logic, 85.1% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Destination Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
================================================================================
Preference: MAXDELAY NET "data_valid_*" 4.000000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "din0_*" 4.000000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "din1_*" 4.000000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout0_d3Z0Z_*" 4.400000 nS ;
8 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 1.786ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout0_d3Z0Z_7 meets
4.400ns delay constraint by 2.614ns
Delays Connection(s)
1.786ns R2C20D.Q1 to R2C20B.M1
Report: 1.786ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout1_d3Z0Z_*" 4.400000 nS ;
8 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 1.066ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout1_d3Z0Z_6 meets
4.400ns delay constraint by 3.334ns
Delays Connection(s)
1.066ns R3C19C.Q0 to R2C19D.M0
Report: 1.066ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_i" 4.400000 nS ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 0.000ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_i meets
4.400ns delay constraint by 4.400ns
Delays Connection(s)
0.000ns R7C17A.F0 to R7C17A.DI0
Report: 0.000ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_dZ0Z_*" 4.400000 nS ;
3 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report: 2.314ns delay on U1_fcram_top/fcram_core_u/fcram_sm_u/dout_val_dZ0Z_0 meets
4.400ns delay constraint by 2.086ns
Delays Connection(s)
1.695ns R13C16A.Q0 to R2C18B.M0
0.747ns R13C16A.Q0 to R13C16A.A1
2.314ns R13C16A.Q0 to R3C17A.CE
1.648ns R13C16A.Q0 to R2C16B.CE
1.724ns R13C16A.Q0 to R2C13C.CE
1.295ns R13C16A.Q0 to R5C16A.CE
1.716ns R13C16A.Q0 to R2C19A.CE
1.371ns R13C16A.Q0 to R4C18A.CE
1.724ns R13C16A.Q0 to R3C13D.CE
1.640ns R13C16A.Q0 to R8C13D.CE
Report: 2.314ns is the maximum delay for this preference.
================================================================================
Preference: MAXDELAY NET "din0_*" 4.400000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: MAXDELAY NET "din1_*" 4.400000 nS ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_dqs_*" MAX 7.250000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.250ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/ddr_io_u/oddrxb_ddr_dqs0 (from pll_clk +)
Destination: Port Pad fcram_dqs_0
Data Path Delay: 2.846ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.591ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.591ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_dqs_0_MGIOL less
2.591ns feedback compensation
2.846ns delay fcram_dqs_0_MGIOL to fcram_dqs_0 less
2.846ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling 0.000ns) meets
7.250ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_dqs_0 by 7.250ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_dqs_0_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T18A.CLK pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Data path fcram_dqs_0_MGIOL to fcram_dqs_0:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.751 IOL_T18A.CLK to IOL_T18A.IOLDO fcram_dqs_0_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T18A.IOLDO to B9.IOLDO U1_fcram_top/ddr_io_u/ddr_dqs_buf_out_0
DOPAD_DEL --- 2.095 B9.IOLDO to B9.PAD fcram_dqs_0
--------
2.846 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T11A.CLK pll_clk
C2OUT_DEL --- 0.751 IOL_T11A.CLK to IOL_T11A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T11A.IOLDO to C9.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 2.095 C9.IOLDO to C9.PAD fcram_clk
--------
5.437 (52.3% logic, 47.7% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: 0.000ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_pdn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.024ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_pdn (from pll_clk -)
Destination: Port Pad fcram_pdn
Data Path Delay: 2.822ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.591ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.591ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_pdn_MGIOL less
2.591ns feedback compensation
2.822ns delay fcram_pdn_MGIOL to fcram_pdn less
2.846ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.024ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_pdn by 5.024ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_pdn_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T10A.CLK pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Data path fcram_pdn_MGIOL to fcram_pdn:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.727 IOL_T10A.CLK to IOL_T10A.IOLDO fcram_pdn_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T10A.IOLDO to B6.IOLDO U1_fcram_top/fpga_io_u/pdn_buf
DOPAD_DEL --- 2.095 B6.IOLDO to B6.PAD fcram_pdn
--------
2.822 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T11A.CLK pll_clk
C2OUT_DEL --- 0.751 IOL_T11A.CLK to IOL_T11A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T11A.IOLDO to C9.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 2.095 C9.IOLDO to C9.PAD fcram_clk
--------
5.437 (52.3% logic, 47.7% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: -0.024ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_csn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.024ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3BX_ddr_csn (from pll_clk -)
Destination: Port Pad fcram_csn
Data Path Delay: 2.822ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.591ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.591ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_csn_MGIOL less
2.591ns feedback compensation
2.822ns delay fcram_csn_MGIOL to fcram_csn less
2.846ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.024ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_csn by 5.024ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_csn_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T8A.CLK pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Data path fcram_csn_MGIOL to fcram_csn:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.727 IOL_T8A.CLK to IOL_T8A.IOLDO fcram_csn_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T8A.IOLDO to B5.IOLDO U1_fcram_top/fpga_io_u/csn_buf
DOPAD_DEL --- 2.095 B5.IOLDO to B5.PAD fcram_csn
--------
2.822 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T11A.CLK pll_clk
C2OUT_DEL --- 0.751 IOL_T11A.CLK to IOL_T11A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T11A.IOLDO to C9.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 2.095 C9.IOLDO to C9.PAD fcram_clk
--------
5.437 (52.3% logic, 47.7% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: -0.024ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_fn" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.024ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_fn (from pll_clk -)
Destination: Port Pad fcram_fn
Data Path Delay: 2.822ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.591ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.591ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_fn_MGIOL less
2.591ns feedback compensation
2.822ns delay fcram_fn_MGIOL to fcram_fn less
2.846ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.024ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_fn by 5.024ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_fn_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T9B.CLK pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Data path fcram_fn_MGIOL to fcram_fn:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.727 IOL_T9B.CLK to IOL_T9B.IOLDO fcram_fn_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T9B.IOLDO to A5.IOLDO U1_fcram_top/fpga_io_u/fn_buf
DOPAD_DEL --- 2.095 A5.IOLDO to A5.PAD fcram_fn
--------
2.822 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T11A.CLK pll_clk
C2OUT_DEL --- 0.751 IOL_T11A.CLK to IOL_T11A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T11A.IOLDO to C9.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 2.095 C9.IOLDO to C9.PAD fcram_clk
--------
5.437 (52.3% logic, 47.7% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: -0.024ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_addr_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
15 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.024ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_addr14 (from pll_clk -)
Destination: Port Pad fcram_addr_14
Data Path Delay: 2.822ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.591ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.591ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_addr_14_MGIOL less
2.591ns feedback compensation
2.822ns delay fcram_addr_14_MGIOL to fcram_addr_14 less
2.846ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.024ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_addr_14 by 5.024ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_addr_14_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T21A.CLK pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Data path fcram_addr_14_MGIOL to fcram_addr_14:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.727 IOL_T21A.CLK to IOL_T21A.IOLDO fcram_addr_14_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T21A.IOLDO to C12.IOLDO U1_fcram_top/fpga_io_u/addr_buf_14
DOPAD_DEL --- 2.095 C12.IOLDO to C12.PAD fcram_addr_14
--------
2.822 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T11A.CLK pll_clk
C2OUT_DEL --- 0.751 IOL_T11A.CLK to IOL_T11A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T11A.IOLDO to C9.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 2.095 C9.IOLDO to C9.PAD fcram_clk
--------
5.437 (52.3% logic, 47.7% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: -0.024ns is the minimum offset for this preference.
================================================================================
Preference: CLOCK_TO_OUT PORT "fcram_ba_*" MAX 5.000000 ns CLKNET "pll_clk" CLKOUT PORT "fcram_clk" ;
2 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 5.024ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FF Q U1_fcram_top/fpga_io_u/OFS1P3DX_ddr_ba1 (from pll_clk -)
Destination: Port Pad fcram_ba_1
Data Path Delay: 2.822ns (100.0% logic, 0.0% route), 2 logic levels.
Clock Path Delay: 2.591ns (0.0% logic, 100.0% route), 1 logic levels.
Constraint Details:
2.591ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_ba_1_MGIOL less
2.591ns feedback compensation
2.822ns delay fcram_ba_1_MGIOL to fcram_ba_1 less
2.846ns delay U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_clk (totaling -0.024ns) meets
5.000ns offset U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_ba_1 by 5.024ns
Physical Path Details:
Clock path U1_fcram_top/sys_clk_pll/ehxpllb_5 to fcram_ba_1_MGIOL:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T12A.CLK pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Data path fcram_ba_1_MGIOL to fcram_ba_1:
Name Fanout Delay (ns) Site Resource
C2OUT_DEL --- 0.727 IOL_T12A.CLK to IOL_T12A.IOLDO fcram_ba_1_MGIOL (from pll_clk)
ROUTE 1 0.000 IOL_T12A.IOLDO to C6.IOLDO U1_fcram_top/fpga_io_u/ba_buf_1
DOPAD_DEL --- 2.095 C6.IOLDO to C6.PAD fcram_ba_1
--------
2.822 (100.0% logic, 0.0% route), 2 logic levels.
Clock out path:
Name Fanout Delay (ns) Site Resource
CLK2OUT_DE --- 0.000 LL3_R27C1.CLKI to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5 (from M5GDCS20_clk_in_c)
ROUTE 342 2.591 L3_R27C1.CLKOP to IOL_T11A.CLK pll_clk
C2OUT_DEL --- 0.751 IOL_T11A.CLK to IOL_T11A.IOLDO fcram_clk_MGIOL
ROUTE 1 0.000 IOL_T11A.IOLDO to C9.IOLDO U1_fcram_top/ddr_io_u/ddr_clk_single
DOPAD_DEL --- 2.095 C9.IOLDO to C9.PAD fcram_clk
--------
5.437 (52.3% logic, 47.7% route), 3 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Feedback path:
Name Fanout Delay (ns) Site Resource
CLKOP_DEL --- 0.000 L3_R27C1.CLKFB to L3_R27C1.CLKOP U1_fcram_top/sys_clk_pll/ehxpllb_5
ROUTE 342 2.591 L3_R27C1.CLKOP to L3_R27C1.CLKFB pll_clk
--------
2.591 (0.0% logic, 100.0% route), 1 logic levels.
PLL3_R27C1.CLKOP attributes: FDEL = 0
Report: -0.024ns is the minimum offset for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "pll_clk" 140.000000 MHz | | |
; | 140.017 MHz| 140.924 MHz| 1
| | |
FREQUENCY NET "clk_in_c" 40.000000 MHz | | |
; | 40.000 MHz| 218.388 MHz| 4
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
prmbdet_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ*" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
prmbdet_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ0" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_read_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ*" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_read_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ0" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_read_dZ0" TO CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
datavalid_inv" 10.000000 ns ; | -| -| 0
| | |
MULTICYCLE FROM CELL | | |
"U1_fcram_top/ddr_io_u/pio_dvalid_gen_0/| | |
pio_data_validZ*" TO CELL | | |
"U1_fcram_top/ddr_io_u/data_validZ0Z_*" | | |
10.000000 ns ; | -| -| 1
| | |
MAXDELAY NET "data_valid_*" 4.000000 nS | | |
; | -| -| 0
| | |
MAXDELAY NET "din0_*" 4.000000 nS ; | -| -| 0
| | |
MAXDELAY NET "din1_*" 4.000000 nS ; | -| -| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut0_d3Z0Z_*" 4.400000 nS ; | 4.400 ns| 1.786 ns| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut1_d3Z0Z_*" 4.400000 nS ; | 4.400 ns| 1.066 ns| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut_val_i" 4.400000 nS ; | 4.400 ns| 0.000 ns| 0
| | |
MAXDELAY NET | | |
"U1_fcram_top/fcram_core_u/fcram_sm_u/do| | |
ut_val_dZ0Z_*" 4.400000 nS ; | 4.400 ns| 2.314 ns| 0
| | |
MAXDELAY NET "din0_*" 4.400000 nS ; | -| -| 0
| | |
MAXDELAY NET "din1_*" 4.400000 nS ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "fcram_dqs_*" MAX | | |
7.250000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 7.250 ns| 0.000 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_pdn" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.024 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_csn" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.024 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_fn" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.024 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_addr_*" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.024 ns| 2
| | |
CLOCK_TO_OUT PORT "fcram_ba_*" MAX | | |
5.000000 ns CLKNET "pll_clk" CLKOUT | | |
PORT "fcram_clk" ; | 5.000 ns| -0.024 ns| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Timing summary:
Timing errors: 0 Score: 0
Constraints cover 4078 paths, 24 nets, and 2757 connections (93.0% coverage)
--------------------------------------------------------------------------------
Generated from the file 'C:\EVALUATION BOARDS\XP\HIGH_END\EVAL_CODE\FCRAM\VHDL\PNR\fcram_vhdl_pnr.twr'