Place and Route Report

PAR: Place And Route ispLever_v50_Production_Build (40).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.
Tue Jun 28 12:36:52 2005

C:/ispTOOLS/ispfpga\bin\nt\par -f fcram_verilog_pnr.p2t
fcram_verilog_pnr_map.ncd fcram_verilog_pnr.dir fcram_verilog_pnr.prf

Preference file: fcram_verilog_pnr.prf.

Cost Table Summary
Level/ Number Timing Run NCD
Cost [ncd] Unrouted Score Time Status
---------- -------- -------- ----- ------------
5_2 * 0 0 51 Complete
5_1 0 154 54 Complete

* : Design saved.

par done!
Lattice Place and Route Report for Design "fcram_verilog_pnr_map.ncd"
Tue Jun 28 12:37:46 2005

Best Par Run
PAR: Place And Route ispLever_v50_Production_Build (40).
Command line: C:/ispTOOLS/ispfpga\bin\nt\par -f fcram_verilog_pnr.p2t
fcram_verilog_pnr_map.ncd fcram_verilog_pnr.dir fcram_verilog_pnr.prf
Preference file: fcram_verilog_pnr.prf.
Placement level-cost: 5-2.
Routing Iterations: 6

Loading design for application par from file
C:/DOCUME~1/jhsin/LOCALS~1/Temp/neo_56.
"fcram_test_top" is an NCD, version 3.0, vendor LATTICE, device LFXP10C,
package FPBGA388, speed 5
Package: Version 1.13.1.2, Status: PRODUCTION
Speed Hardware Data: version 1.169
Device utilization summary:

PIO 81/280 28% used
81/244 33% bonded

IOLOGIC 31/280 11% used
DQS 1/16 6% used
DQSDLL 1/2 50% used
SLICE 484/4864 9% used

GSR 1/1 100% used
PLL3 1/4 25% used

Number of Signals: 1204
Number of Connections: 2952
The following 3 signals are selected to use the primary clock routing resources:
pll_clk (driver: U1_fcram_top/sys_clk_pll/ehxpllb_5, clk load #: 338)
U1_fcram_top/sys_clk_0 (driver: U1_fcram_top/sys_clk_pll/ehxpllb_5, clk load #: 29)
clk_in_c (driver: clk_in, clk load #: 19)

The following 1 signal is selected to use the DCS clock routing resource:
clk_in_c (driver: clk_in, clk load #: 19)

The following 1 signal is selected to use the secondary clock routing resource:
rst_n_c (driver: rst_n, clk load #: 0, sr load #: 139, ce load #: 12)

WARNING - par: Secondary clock driver 'rst_n' is located at AB2 (not a
dedicated clock PIO). Please check if user already located this
comp, or this comp has dedicated connection with PLLs which must
be placed at its corresponding dedicated PIOs.
Signal rst_n_c is selected as Global Set/Reset.
Starting Placer Phase 0.
............
Finished Placer Phase 0. REAL time: 2 secs

Starting Placer Phase 1.
Placer score = 1592601.
......................................
Placer score = 1462685.
Finished Placer Phase 1. REAL time: 41 secs

Starting Placer Phase 2.
.
Placer score = 1453241
Finished Placer Phase 2. REAL time: 44 secs

Total placer CPU time: 43 secs

Dumping design to file fcram_verilog_pnr.dir/5_2.ncd.

0 connections routed; 2955 unrouted.
Starting router resource preassignment
WARNING - par: The driver of secondary clock net rst_n_c is not placed on
one of the PIO sites which are dedicated for secondary clocks.
This secondary clock will be routed through general routing
resource and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 48 secs
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
2955 successful; 0 unrouted; (1061) real time: 50 secs
Dumping design to file fcram_verilog_pnr.dir/5_2.ncd.
End of iteration 2
2955 successful; 0 unrouted; (0) real time: 50 secs
Dumping design to file fcram_verilog_pnr.dir/5_2.ncd.
Constraints are met.
Total CPU time 48 secs
Total REAL time: 50 secs
Completely routed.
End of route. 2955 routed (100.00%); 0 unrouted.
Checking DRC ...
No errors found.
Timing score: 0

Total REAL time to completion: 51 secs

All signals are completely routed.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2005 Lattice Semiconductor Corporation, All rights reserved.

Generated from the file 'C:\EVALUATION BOARDS\XP\HIGH_END\EVAL_CODE\FCRAM\VERILOG\PNR\fcram_verilog_pnr.par'