The following describes the function of the test pattern project (ispLEVER design project) found in this .zip file. All the project files for the ispLEVER design project are included in this .zip. 

For more information on the ispLEVER design software, please see:
www.latticesemi.com/software

This test pattern is loaded onto all new LatticeXP Advanced Evaluation boards when shipped.

The design uses the 33MHz on board oscillator to clock a 23-bit up counter.

The MSbit of the upcounter is used as a source to clock a down counter, essentially "slowing down" the clock to a human-readable frequency of about 2Hz.

The down counter is connected to the appropriate external IOs, which drive the bank of LEDs.

The down counter output is also passed to combinatorial logic used
to translate the low nibble of the counter into 7-segment count values.

Additionally, DIP switch 1 is connected to toggle the 7-segment decimal point.
