Lattice Semiconductor TN1078 describes using SPI Flash memories in 
conjunction with the EC/ECP FPGA.  The files enclosed provide reference 
material for implementing the programming techniques described in 
TN1078.  Download and refer to TN1078 for more information on using SPI 
Flash memories with Lattice EC/ECP FPGA's.

The .zip file contains 6 files:

1) readme.txt -- this document

2) SPITOP.ngo -- Soft SPI Interface netlist, allows JTAG to communicate 
with the SPI Serial Flash pins

   This file is instantiated as a HDL black box.  It is important to 
   make this file read-only (prevents ispLever File->Cleanup command 
   from erasing the file).

3) simple_top.v -- a simple netlist instantiation example in verilog

4) simple_top.vhd -- a simple netlist instantiation example in VHDL

5) mux_top.v -- an example, in verilog, of the instantiated netlist 
muxed with an external SPI interface

6) mux_top.vhd -- an example, in VHDL, of the instantiated netlist muxed 
with an external SPI interface

Create a new Project using ispLEVER.  Place SPITOP.ngo and the desired 
example source code in the top level directory and import the source 
file.  Be sure to select an EC or ECP device and package.  In the left 
pane of the project navigator you should see the selected source code 
(called top) under the device name and you should see SPITOP under the 
source code (in a parent-child directory structure).

Note:  When using VHDL SPITOP will be represented by a "red question 
mark" icon.  This is normal.

Next, open the contraint editor by double-clicking on Pre-Map Preference 
Editor.  Click on the Global Contraints tab and make sure that 
Persistent is OFF and Config Mode is NONE.  Click on the Pin Attributes 
tab and reserve the proper pins based on the package you selected (refer 
to TN1078).

If you are using a version of ispLEVER prior to 4.2 SP1 then you will 
also need to turn off Persistent in Generate Bitstream Data.  You do 
this from ispLEVER's project navigator page; scroll down the right pane, 
right click on Generate Bitstream Data, select Properties, and click on 
Persistent.

During code compilation you may ignore warnings from the Soft SPI 
Interface code that resemble the following:

WARNING - ngdbuild: logical net 'GNDZ0' has no driver 
WARNING - ngdbuild: logical net 'GNDZ0' has no load 
WARNING - ngdbuild: logical net 'VCCZ0' has no driver 
WARNING - ngdbuild: logical net 'VCCZ0' has no load 
WARNING - ngdbuild: logical net 'u1/GNDZ2' has no driver 
WARNING - ngdbuild: logical net 'u1/GNDZ2' has no load 
WARNING - ngdbuild: logical net 'u1/VCCZ2' has no driver 
WARNING - ngdbuild: logical net 'u1/VCCZ2' has no load 
WARNING - ngdbuild: logical net 'u1/ER1_inst/JRTI1' has no load 
WARNING - ngdbuild: logical net 'u1/ER1_inst/JRTI2' has no load 
WARNING - map: logical net 'GNDZ0' has no driver 
WARNING - map: logical net 'VCCZ0' has no driver 
WARNING - map: logical net 'u1/GNDZ2' has no driver 
WARNING - map: logical net 'u1/VCCZ2' has no driver

If you have any technical questions, please contact Lattice technical 
support at: 

   1-800-Lattice [528-8423] North America 1-408-826-6002 Outside North 
   America techsupport@latticesemi.com

Or visit our website at:

http://www.latticesemi.com
