Designing a Fast Page Mode DRAM Controller
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File List

1.	/RD1014/docs/rd1014.pdf                            --> Designing a Fast Page Mode DRAM Controller document
		/RD1014/docs/rd1014_readme.txt                     --> Read me file (this file)

2.	/RD1014/Project/rd1014.h													 --> Project file

		/RD1014/Project/rd1014.lci												 --> Preference constraint file for ispLEVER Classic
		/RD1014/Project/fpdramtb_tffa.udo     						 --> Functional verilog simulation script for ispLEVER Classic
		/RD1014/Project/fpdramtb_tfa.udo      						 --> Timing verilog simulation script for ispLEVER Classic
		/RD1014/Project/fpdramtb_vhdaf.udo       					 --> Functional vhdl simulation script for ispLEVER Classic
		/RD1014/Project/fpdramtb_vhda.udo        					 --> Timing vhdl simulation script for ispLEVER Classic

		/RD1014/Project/rd1014.lpf              					 --> Preference constraint file for ispLEVER8.1 SP01 and diamond
		/RD1014/Project/fpdramtb_tff.udo        					 --> Functional verilog simulation script for ispLever8.1 SP01
		/RD1014/Project/fpdramtb_tf.udo         					 --> Timing verilog simulation script for ispLever8.1 SP01
		/RD1014/Project/fpdramtb_tfr.udo        					 --> Post Route Functional verilog simulation script for ispLever8.1 SP01

		/RD1014/Project/fpdramtb_vhdf.udo          				 --> Functional vhdl simulation script for ispLever8.1 SP01
		/RD1014/Project/fpdramtb_vhd.udo           				 --> Timing vhdl simulation script for ispLever8.1 SP01
		/RD1014/Project/fpdramtb_vhdr.udo          				 --> Post Route Functional vhdl simulation script for ispLever8.1 SP01

3.  /RD1014/Simulation/verilog/rtl_verilog.do					 --> RTL simulation script file for verilog
    /RD1014/Simulation/verilog/timing_verilog.do			 --> Timing simulation script file for verilog
    /RD1014/Simulation/vhdl/rtl_vhdl.do								 --> RTL simulation script file for vhdl
    /RD1014/Simulation/vhdl/timing_vhdl.do						 --> Timing simulation script file for vhdl

4.  /RD1014/source/verilog/fpdram.v                    --> Verilog source file - top level
	  /RD1014/source/verilog/Decoder.v                   --> Verilog source file
	  /RD1014/source/verilog/sm.v                        --> Verilog source file
	  /RD1014/source/verilog/Mux.v                       --> Verilog source file

	  /RD1014/source/vhdl/fpdram.vhd                     --> Vhdl source file - top level
	  /RD1014/source/vhdl/Decoder.vhd                    --> Vhdl source file
	  /RD1014/source/vhdl/sm.vhd                         --> Vhdl source file
	  /RD1014/source/vhdl/Mux.vhd                        --> Vhdl source file

5.	/RD1014/testbench/verilog/fpdramtb.v               --> Testbench for verilog simulation - top
		/RD1014/testbench/vhdl/fpdramtb.vhd                --> Testbench for vhdl simulation - top

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Important notes:
1. Unzip the RD1014_revyy.y.zip file using the existing folder names.
2. If there is a lpf file or lci file available for the reference design,copy the contents of the provided lpf file to the <project_name>.lpf file
   under your newly created XO or FPGA project, or the contents of the provided lci file to the <project_name>.lci under your cpld project.
3. If there is sty file (strategy file for Diamond) available for the design, go to File List tab on the left side of the GUI. Right click on
   Strategies >> Add >> Existing File. Then right click on the imported file name and select "Set as Active Strategy".
4. The *.do simulation scripts are location specific. User must modify the paths to point to their library location or Diamond project paths.
5. The *.udo simulation scripts are for ispLEVER8.1 SP01 and ispLEVER Classic simulation.
	 5.1 If user selects the verilog source and ispLEVER8.1 SP01 for his project,he needs to copy 2 files(fpdramtb_tff.udo,fpdramtb_tf.udo )to the project
	 		 directory where *.syn resides.
	 5.2 If user selects the vhdl source and ispLEVER8.1 SP01 for his project, he needs to copy 2 files(fpdramtb_vhdf.udo,fpdramtb_vhd.udo) to the project
	     directory where *.syn resides.
   5.3 If user selects the verilog source and ispLEVER classic for his project,he needs to copy 2 files(fpdramtb_tffa.udo,fpdramtb_tfa.udo )to the project
       directory where *.syn resides.
   5.4 If user selects the vhdl source and ispLEVER classic for his project, he needs to copy 2 files(fpdramtb_vhdaf.udo,fpdramtb_vhda.udo)to the project
   		 directory where *.syn resides.
6. If user selects ispLSI5000VE device as his targeted device, he needs to change the Fmax constraint setting in the rd1014.lci. The Fmax for this device is
   100MHz.

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How to create a ispLEVER or ispLEVER Classic project:
1. Create a new ispLEVER or ispLever Classic project;
2. Use RD1014.pdf to see which device /speedgrade should be selected to achieve the desired timing result;
3. Make sure provided lpf life or lci file is used in the current directory.

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How to run simulation from ispLEVER or ispLEVER Classic project:
1. In the Project Navigator, highlight the testbench\<verilog or vhdl>\fpdramtb.v(vhd) file on the left-side panel,user will see 3 simulation options on
   the right panel.
2. For functional simulation, double click on verilog or vhdl Functional Simulation with Aldec Active-HDL. Aldec simulator will be brought up,click yes
   to overwrite the existing file.
3. Functional simulation will run until complete. user will see a script shown in the console panel like this:

add wave fpdramtb/clk
add wave fpdramtb/uut/u2/ps
add wave fpdramtb/a
add wave fpdramtb/asb
add wave fpdramtb/siz1
add wave fpdramtb/siz0
add wave fpdramtb/rwb
add wave fpdramtb/resetb
add wave fpdramtb/ras1o
add wave fpdramtb/ras2o
add wave fpdramtb/ucaso
add wave fpdramtb/lcaso
add wave fpdramtb/weo
add wave fpdramtb/dsack1o
add wave fpdramtb/dsack0o
add wave fpdramtb/ma
add wave fpdramtb/uut/u2/refreq
add wave fpdramtb/uut/u2/refack
run 16270 ns
# KERNEL:                  150 start Random Mode Word READ
# KERNEL:                  310 start Random Mode Word Write
# KERNEL:                  590 start Random Upper Byte READ
# KERNEL:                  750 start Random Mode Lower Byte Write
# KERNEL:                 1030 start Random Mode Word READ
# KERNEL:                 1190 start Random Mode Word Write
# KERNEL:                 1470 start Random Mode Upper Byte READ
# KERNEL:                 1630 Random Mode Lower Byte Write
# KERNEL:                 1910 Page mode access to bank 1
# KERNEL:                 2430 Page mode access to bank 2
# KERNEL:                15750 CAS-Before-RAS Refresh
# RUNTIME: RUNTIME_0068 fpdramtb.v (266): $finish called.
# KERNEL: Time: 16270 ns,  Iteration: 0,  TOP instance,  Process: @INITIAL#91_1@.

4. For timing simulation, double click on verilog or vhdl Post-Route Timing Simulation with Aldec Active-HDL. Similar message will be shown in the
	 console panel of the Aldec Active-HDL simulator.

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How to create a project in Diamond:
1. Unzip the RD1014_revyy.y.zip file using the existing folder names, where yy.y is the current version of the zip file.
2. Bring up Diamond software, in the GUI, select File >> New Project, click Next.
3. In the New Project popup, select the Project location and provide a Project name, click Next.
   Note: default project location is \RD1014\project\<device_family>_diamond\.
         default project name is rd1014.
4. Add the necessary source files from the RD1014\source directory,click Next.
5. Select device, speedgrade,package, click Next.
6. Click Finish. Now the project is successfully created.
7. If there is lpf file available for the reference design, go to File List tab on the left side of the GUI. Right click on constraint File >> Add >> Existing File.
   Then right click on the imported file name and select "Set as Active Preference file".
8. If there is sty file available for the reference design, go to File List tab on the left side of the GUI. Right click on Strategies >> Add >> Existing File.
   Then right click on the imported file name and select "Set as Active Strategy".

How to run simulation under Diamond:
1. Go to \RD1014\simulation directory, open rtl_<language>.do or timing_<language>.do to modify the paths to point to current directory.
	 1.1 create the directory location for your simulation, \RDxxxx\simulation\<language>\rtl or \RDxxxx\simulation\<language>\timing are default locations.

2. Bring up Active-HDL from Diamond environment. Click cancel when pop up windows come up.
3. For functional simulation, go to Tools >> Execute Macros, browse to \RD1014\simulation\<language>\rtl directory, select rtl_<language>.do. This
   should run simulation all the way to the end. Error in this stage is often caused by incorrect paths for source / testbench, etc.
4. For timing simulation, go to Tools >> Execute Macros, browse to \RD1014\simulation\<language>post_route directory, select timing_<language>.do.
   Make sure the post-route netlist file is available in the correct location. This should run simulation all the way to the end. Error in this stage
   is often caused by incorrect paths for source / testbench, etc.

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How to run Fit/Place and Route, JEDEC generation, and Timing Analysis in ispLEVER:
1. Highlight the device on the left-side panel of the Project Navigator (ispLEVER). On the right-side panel,
   a. if it is 4000ZE/5000VE/M4A3 device, double click on Fit Design. This will bring the deisgn through fitting.
   b. if it is XO/XO2/XP2/ device,double click on Place and Route Design. This will bring the design through synthesis, mapping,and place and route.
2. Highlight the device on the left-side panel of the Project Navigator. On the right-side panel, double click on.
   a. JEDEC file for 4000ZE/5000VE/M4A3 design flow.
   b. Generate Data File (JEDEC) for XO or FPGA deisgn flow. This will generate the jedec file for the design.
3. For timing information, double click on
	 a. Timing Analysis for 4000ZE/5000VE/M4A3 deisgn,
   b. Place and Route Trace Report for XO or FPGA design to get the timing analysis result.

How to run Place and Route, JEDEC generation, and Timing Analysis in Diamond:
1. Double click the process in the Process panel to run the process, e.g. double click on Place and Route design.
2. Double click on Export File >> JEDEC file to generate the jedec files.
3. Run the Place and Route Trace, then go to Report tab to view the TRACE report.
