          HDLC Reference Design
===============================================================================
File List ( 82 files )
1. /docs/rd1009.pdf                         			 						--> design document
   /docs/rd1009_readme.txt                  			 						--> this document
2. /netlist/HDLC_RECEIVE_CCITT.bl1 				 			 							--> CRC_CCITT receive module netlist
   /netlist/HDLC_RECEIVE_CRC16.bl1         			 							--> CRC16 receive module netlist
   /netlist/HDLC_RECEIVE_CRC32.bl1         			 							--> CRC32 receive module netlist
   /netlist/HDLC_TRANSMIT_CCITT.bl1        			 							--> CRC_CCITT transmit module netlist
   /netlist/HDLC_TRANSMIT_CRC16.bl1        			 							--> CRC16 transmit module netlist
   /netlist/HDLC_TRANSMIT_CRC32.bl1        			 							--> CRC32 transmit module netlist
3. /project/4000/sc/crc16/HDLC_4K_CRC16.syn   	 							--> project file
   /project/4000/sc/crc16/HDLC_4K_CRC16.lct   	 							--> preference file
   /project/4000/sc/crc16/sc_hdlc_tb_vhda.udo    							--> Timing Simulation script(active_hdl)
	 /project/4000/sc/crc16/sc_hdlc_tb_vhdaf.udo   							--> Functional Simulation script(active_hdl)
	 /project/4000/sc/crc16/sc_hdlc_tb_vhd.udo    							--> Timing Simulation script(modelsim)
	 /project/4000/sc/crc16/sc_hdlc_tb_vhdf.udo   							--> Functional Simulation script(modelsim)
   /project/4000/sc/crc32/HDLC_4K_CRC32.syn   			 					--> project file
   /project/4000/sc/crc32/HDLC_4K_CRC32.lct   			 					--> preference file
   /project/4000/sc/crc32/sc_hdlc_tb_vhda.udo   		 					--> Timing Simulation script(active_hdl)
	 /project/4000/sc/crc32/sc_hdlc_tb_vhdaf.udo   	 						--> Functional Simulation script(active_hdl)
	 /project/4000/sc/crc32/sc_hdlc_tb_vhd.udo   		 					  --> Timing Simulation script(modelsim)
	 /project/4000/sc/crc32/sc_hdlc_tb_vhdf.udo   	 						--> Functional Simulation script(modelsim)
	 /project/4000/sc/crc_ccitt/HDLC_4K_CRC_CCITT.syn   				--> project file
   /project/4000/sc/crc_ccitt/HDLC_4K_CRC_CCITT.lct   				--> preference file
   /project/4000/sc/crc_ccitt/sc_hdlc_tb_vhda.udo							--> Timing Simulation script(active_hdl)
   /project/4000/sc/crc_ccitt/sc_hdlc_tb_vhdaf.udo  					--> Functional Simulation script(active_hdl)
   /project/4000/sc/crc_ccitt/sc_hdlc_tb_vhd.udo							--> Timing Simulation script(modelsim)
   /project/4000/sc/crc_ccitt/sc_hdlc_tb_vhdf.udo  					  --> Functional Simulation script(modelsim)
   /project/4000ZE/sc/crc16/HDLC_4KZE_CRC16.syn   						--> project file
   /project/4000ZE/sc/crc16/HDLC_4KZE_CRC16.lct   						--> preference file
   /project/4000ZE/sc/crc16/sc_hdlc_tb_vhda.udo   						--> Timing Simulation script(active_hdl)
   /project/4000ZE/sc/crc16/sc_hdlc_tb_vhdaf.udo   	 					--> Functional Simulation script(active_hdl)
   /project/4000ZE/sc/crc16/sc_hdlc_tb_vhd.udo   						  --> Timing Simulation script(modelsim)
   /project/4000ZE/sc/crc16/sc_hdlc_tb_vhdf.udo   	 					--> Functional Simulation script(modelsim)
   /project/4000ZE/sc/crc32/HDLC_4KZE_CRC32.syn   						--> project file
   /project/4000ZE/sc/crc32/HDLC_4KZE_CRC32.lct   						--> preference file
   /project/4000ZE/sc/crc32/sc_hdlc_tb_vhda.udo   						--> Timing Simulation script    (active_hdl)
   /project/4000ZE/sc/crc32/sc_hdlc_tb_vhdaf.udo   	 					--> Functional Simulation script(active_hdl)
   /project/4000ZE/sc/crc32/sc_hdlc_tb_vhd.udo   						  --> Timing Simulation script    (modelsim)
   /project/4000ZE/sc/crc32/sc_hdlc_tb_vhdf.udo   	 					--> Functional Simulation script(modelsim)
   /project/4000ZE/sc/crc_ccitt/HDLC_4KZE_CRC_CCITT.syn   	 	--> project file
   /project/4000ZE/sc/crc_ccitt/HDLC_4KZE_CRC_CCITT.lct   	 	--> preference file
   /project/4000ZE/sc/crc_ccitt/sc_hdlc_tb_vhda.udo   				--> Timing Simulation script    (active_hdl)
   /project/4000ZE/sc/crc_ccitt/sc_hdlc_tb_vhdaf.udo  				--> Functional Simulation script(active_hdl)
   /project/4000ZE/sc/crc_ccitt/sc_hdlc_tb_vhd.udo   				  --> Timing Simulation script    (modelsim)
   /project/4000ZE/sc/crc_ccitt/sc_hdlc_tb_vhdf.udo  				  --> Functional Simulation script(modelsim)
   /project/5000VG/sc/crc16/HDLC_5KVG_CRC16.syn   			 			--> project file
   /project/5000VG/sc/crc16/HDLC_5KVG_CRC16.lct   			 			--> preference file
   /project/5000VG/sc/crc16/sc_hdlc_tb_vhda.udo   		 				--> Timing Simulation script    (active_hdl)
   /project/5000VG/sc/crc16/sc_hdlc_tb_vhdaf.udo   	 					--> Functional Simulation script(active_hdl)
   /project/5000VG/sc/crc16/sc_hdlc_tb_vhd.udo   		 					--> Timing Simulation script    (modelsim)
   /project/5000VG/sc/crc16/sc_hdlc_tb_vhdf.udo   	 					--> Functional Simulation script(modelsim)
   /project/5000VG/sc/crc32/HDLC_5KVG_SC_CRC32.syn   			 		--> project file
   /project/5000VG/sc/crc32/HDLC_5KVG_SC_CRC32.lct   			 		--> preference file
   /project/5000VG/sc/crc32/sc_hdlc_tb_vhda.udo   		 				--> Timing Simulation script    (activel_hdl)
   /project/5000VG/sc/crc32/sc_hdlc_tb_vhdaf.udo   	 					--> Functional Simulation script(activel_hdl)
   /project/5000VG/sc/crc32/sc_hdlc_tb_vhd.udo   		 					--> Timing Simulation script    (modelsim)
   /project/5000VG/sc/crc32/sc_hdlc_tb_vhdf.udo   	 					--> Functional Simulation script(modelsim)
   /project/5000VG/sc/crc_ccitt/HDLC_5KVG_SC_CRC_CCITT.syn   	--> project file
   /project/5000VG/sc/crc_ccitt/HDLC_5KVG_SC_CRC_CCITT.lct   	--> preference file
   /project/5000VG/sc/crc_ccitt/sc_hdlc_tb_vhda.udo   				--> Timing Simulation script    (active_hdl)
   /project/5000VG/sc/crc_ccitt/sc_hdlc_tb_vhdaf.udo  				--> Functional Simulation script(active_hdl)
   /project/5000VG/sc/crc_ccitt/sc_hdlc_tb_vhd.udo   				  --> Timing Simulation script    (modelsim)
   /project/5000VG/sc/crc_ccitt/sc_hdlc_tb_vhdf.udo  				  --> Functional Simulation script(modelsim)
   /project/5000VG/mc/crc16/HDLC_5KVG_MC_CRC16.syn   			 		--> project file
	 /project/5000VG/mc/crc16/HDLC_5KVG_MC_CRC16.lct   			 		--> preference file
	 /project/5000VG/mc/crc16/sc_hdlc_tb_vhda.udo   		 				--> Timing Simulation script    (active_hdl)
	 /project/5000VG/mc/crc16/sc_hdlc_tb_vhdaf.udo   	 					--> Functional Simulation script(active_hdl)
	 /project/5000VG/mc/crc16/sc_hdlc_tb_vhd.udo   		 				  --> Timing Simulation script    (modelsim)
	 /project/5000VG/mc/crc16/sc_hdlc_tb_vhdf.udo   	 					--> Functional Simulation script(modelsim)
		 /project/5000VG/mc/crc_ccitt/HDLC_5KVG_MC_CRC_CCITT.syn  --> project file
	 /project/5000VG/mc/crc_ccitt/HDLC_5KVG_MC_CRC_CCITT.lct   	--> preference file
	 /project/5000VG/mc/crc_ccitt/sc_hdlc_tb_vhda.udo   				--> Timing Simulation script    (active_hdl)
	 /project/5000VG/mc/crc_ccitt/sc_hdlc_tb_vhdaf.udo  				--> Functional Simulation script(active_hdl)
	 /project/5000VG/mc/crc_ccitt/sc_hdlc_tb_vhd.udo   				  --> Timing Simulation script    (modelsim)
	 /project/5000VG/mc/crc_ccitt/sc_hdlc_tb_vhdf.udo  				  --> Functional Simulation script(modelsim)
4. /source/MC_HDLC_top.vhd														 				--> Multi-channel hdlc
   /source/SC_HDLC_top.vhd                            				--> Single-channel hdlc
   /source/rx_demux.vhd                               				--> Rx-demux module
   /source/tx_mux.vhd                                 				--> Tx-mux module
5. /testbench/mc_hdlc_tb.vhd											 						--> Multi-channel testbench
	 /testbench/sc_hdlc_tb.vhd	                     						--> Single-channel testbench
	 /testbench/hdlc_lib_active_hdl.zip													--> Functional simulation library with active_hdl
	 /testbench/hdlc_lib_modelsim.zip														--> Functional simulation library with Modelsim

Attention:
For this application,the default top file selects CRC16 polynomial as the receiving and transmitting
CRC polynomial. If you need the other CRC polynomial, you must replace or comment out some
code and uncomment your selected CRC polynomial in the top file. For example, if you need CRC_CCITT,
you must comment CRC16 code and uncomment CRC_CCITT in the SC_HDLC_top or MC_HDLC_top file.

Fit design with ispLEVER Classic1.3
1. Unzip the RD1009_rev03.1.zip file using the existing folder names.
2. Open the ispLEVER Classic1.3 Project Navigator.
3. From the 'File' menu, select 'Open Project' and browse to the desired project file.
4. Select the expected device family,for example, selecting 4000ZE.
5. Select the expected CRC polynomial,for example selecting CRC16.
6. Double click *.syn file,for example HDLC_4KZE_CRC16.syn,If select 5000VG device, the software will
   suggest you to replace this device with another family, you should select No in this case.
7. Add receive netlist and transmit netlist file under directory netlist to the sub-directory /device/sc/
   crc(16,32,ccitt) under your project directory.For example,copy HDLC_RECEIVE_CRC16.bl1 and
   HDLC_TRANSMIT_CRC16.bl1 to /project/4000ZE/sc/CRC16 directory.
8. Highlight the device on the left panel of the Project Navigator. In the right-hand panel, double
	 -click 'Fit Design'.

Running simulation
1.If user prefer active_hdl,they need create work directory in the project directory where *.syn resides.
	If user prefer modelsim, they need creat hdlc_lib directory in the project directory where *.syn resides.
2.If users use active_hdl,they can unzip hdlc_lib_active_hdl.zip file into the work directory as the simulation library;
	If users prefer modelsim,they can unzip hdlc_lib_modelsim.zip into hdlc_lib directory as the simulation library.
3.In the Project Navigator, highlight ..\..\..\..\sc_hdlc_tb.vhd in the left up window.
4.For functional simulation, double-click 'Aldec VHDL Functional Simulation'.
	The simulator will be brought up. If prompted, click yes to overwrite the existing file.
5.For timing simulation, double-click 'Aldec VHDL Timing Simulation'.
