    --------------------------------------------------------------------------------
    Lattice TRACE Report, Version ispLever_v50_Production_Build (40)
    Mon May 09 18:23:33 2005

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 1 -o checkpnt.twr ddr_vhdl_pnr.ncd ddr_vhdl_pnr.prf
    Design file:     ddr_vhdl_pnr.ncd
    Preference file: ddr_vhdl_pnr.prf
    Device,speed:    LFEC20E,5
    Report level:    verbose report, limited to 1 item per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY NET "pll_clk" 210.000000 MHz (0 errors)
                4096 items scored, 0 timing errors detected.
    Report:  212.766MHz is the maximum frequency for this preference.

    FREQUENCY NET "clk_in_c" 40.000000 MHz (0 errors)
                181 items scored, 0 timing errors detected.
    Report:  233.645MHz is the maximum frequency for this preference.

    BLOCK PATH FROM PORT "rst_n" (0 errors)
                64 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "pll_clk" 210.000000 MHz ;
                4096 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 0.061ns

     Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

       Source:         FF         Q              U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/row_addr_lat_6  (from pll_clk +)
       Destination:    FF         Data in        U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_row_1  (to pll_clk +)

       Delay:               4.584ns  (34.8% logic, 65.2% route), 5 logic levels.

     Constraint Details:

           4.584ns physical path delay SLICE_559 to SLICE_895 meets
           4.761ns delay constraint less
           0.000ns skew and
           0.116ns M_SET requirement (totaling 4.645ns) by 0.061ns

     Physical Path Details:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.363    R14C30C.CLK to     R14C30C.Q0 SLICE_559 (from pll_clk)
    ROUTE         1     1.796     R14C30C.Q0 to     R15C30D.A0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/row_addr_latZ0Z_6
    A0TOFCO_DE  ---     0.572     R15C30D.A0 to    R15C30D.FCO SLICE_33
    ROUTE         1     0.000    R15C30D.FCO to    R15C31A.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq7_6_n
    FCITOFCO_D  ---     0.092    R15C31A.FCI to    R15C31A.FCO SLICE_32
    ROUTE         1     0.000    R15C31A.FCO to    R15C31B.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq9_8_n
    FCITOCOUT_  ---     0.327    R15C31B.FCI to   R15C31B.OFX1 SLICE_31
    ROUTE         1     0.711   R15C31B.OFX1 to     R16C30A.D0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq11_10_n
    CTOF_DEL    ---     0.241     R16C30A.D0 to     R16C30A.F0 SLICE_576
    ROUTE         2     0.482     R16C30A.F0 to     R16C30C.M0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/N_882_iZ0 (to pll_clk)
                      --------
                        4.584   (34.8% logic, 65.2% route), 5 logic levels.

     Clock Skew Details:

     Source Clock:
               Delay              Connection
              2.911ns PLL3_R40C1.CLKOP to R14C30C.CLK

     Destination Clock :
               Delay              Connection
              2.911ns PLL3_R40C1.CLKOP to R16C30C.CLK

    Report:  212.766MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY NET "clk_in_c" 40.000000 MHz ;
                181 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 20.720ns

     Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

       Source:         FF         Q              wait_200us_count3_2_F1  (from E5GDCS11_clk_in_c +)
       Destination:    FF         Data in        waited_200us  (to E5GDCS11_clk_in_c +)

       Delay:               4.163ns  (26.1% logic, 73.9% route), 4 logic levels.

     Constraint Details:

           4.163ns physical path delay SLICE_64 to SLICE_845 meets
          25.000ns delay constraint less
           0.000ns skew and
           0.117ns DIN_SET requirement (totaling 24.883ns) by 20.720ns

     Physical Path Details:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.363    R18C45B.CLK to     R18C45B.Q0 SLICE_64 (from E5GDCS11_clk_in_c)
    ROUTE         2     1.330     R18C45B.Q0 to     R17C45A.C0 wait_200us_count_2
    CTOF_DEL    ---     0.241     R17C45A.C0 to     R17C45A.F0 SLICE_1074
    ROUTE         1     1.016     R17C45A.F0 to     R17C47C.A1 G_2Z0Z_12
    CTOF_DEL    ---     0.241     R17C47C.A1 to     R17C47C.F1 SLICE_871
    ROUTE         1     0.731     R17C47C.F1 to     R19C46A.D0 G_1_sZ0
    CTOF_DEL    ---     0.241     R19C46A.D0 to     R19C46A.F0 SLICE_845
    ROUTE         1     0.000     R19C46A.F0 to    R19C46A.DI0 GZ0Z_1 (to E5GDCS11_clk_in_c)
                      --------
                        4.163   (26.1% logic, 73.9% route), 4 logic levels.

     Clock Skew Details:

     Source Clock:
               Delay              Connection
              0.447ns    URDCS1.DCSOUT to R18C45B.CLK

     Destination Clock :
               Delay              Connection
              0.447ns    URDCS1.DCSOUT to R19C46A.CLK

    Report:  233.645MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: BLOCK PATH FROM PORT "rst_n" ;
                64 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

     Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

       Source:         Port       Pad            rst_n
       Destination:    DQSDLL     Port           U1_ddr_sdram_mem_top/U1_DQSDLL  (to pll_clk +)

       Delay:               7.203ns  (11.1% logic, 88.9% route), 2 logic levels.

     Constraint Details:

           7.203ns physical path delay rst_n to U1_ddr_sdram_mem_top/U1_DQSDLL
           1.400ns RST_SET requirement

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.556         K1.PAD to       K1.PADDI rst_n
    ROUTE       666     5.100       K1.PADDI to      R2C33C.A0 rst_n_c
    CTOF_DEL    ---     0.241      R2C33C.A0 to      R2C33C.F0 SLICE_987
    ROUTE         1     1.306      R2C33C.F0 to       TDLL.RST rst_n_c_iZ0 (to pll_clk)
                      --------
                        7.203   (11.1% logic, 88.9% route), 2 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "pll_clk" 210.000000 MHz  |             |             |
    ;                                       |  210.040 MHz|  212.766 MHz|     5
                                            |             |             |
    FREQUENCY NET "clk_in_c" 40.000000 MHz  |             |             |
    ;                                       |   40.000 MHz|  233.645 MHz|     4
                                            |             |             |
    BLOCK PATH FROM PORT "rst_n" ;          |            -|            -|     2
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Timing summary:

    Timing errors: 0  Score: 0

    Constraints cover 5681 paths, 4 nets, and 5650 connections (84.2% coverage)

    --------------------------------------------------------------------------------

    Generated from the file 'C:\EVALUATION BOARDS\EC\HIGH_END\EVAL_CODE\DDR\VHDL\PNR\ddr_vhdl_pnr.twr'