// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2003 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                         FILE DETAILS
// Project          : DDR SDRAM Controller
// File             : ddrct_gen_e2_1_001.v
// Title            : Top level file for the DDRSDRAM Controller 
// Dependencies     : ddr_sdram_mem_params.v, 
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Mod. Date        : Sept 09, 2003
// Changes Made     : Initial Creation
//
// =============================================================================

module ddrct_gen_e2_1_001 (

   // Clock and reset
   clk,
   rst_n,

   // Inputs from the FPGA Bridge
   fb_cmd,
   fb_addr,
   fb_cmd_valid,
   fb_burst_length,
   fb_init_start,
   fb_write_data,
   fb_data_mask,

   data_valid_tap,
   //dataout_valid,
   data_valid_tmp,
   cas_latency,

   // Inputs from the Configuration module
   tras,
   trc,
   trcd,
   trrd,
   trfc,
   trp,
   tmrd,
   twr,
   trefi,
   ar_burst_en,

   `ifdef DDR2_MODE
       trtp,
       twtr,
       tckp,
   `else
       ext_reg_en,
       fb_burst_term,
   `endif

   // Outputs to the FPGA Bridge
   fb_cmd_rdy,
   init_done,
   fb_data_rdy,

   // Outputs to the I/O Bridge
   ddr_cke,
   ddr_ras_n,
   ddr_cas_n,
   ddr_we_n,
   ddr_cs_n,

   `ifdef DDR2_MODE
       ddr_odt,
   `endif

   pio_read,
   read_command,
   dv_bl_cycles,
   dv_cs_csm_is_rd,
   rd_cmd_pulse,

   ddr_addr,
   ddr_ba,
   ddr_dqs_out,
   ddr_write_data,
   ddr_DM,
   ddr_write_valid_early,
   ddr_write_valid
) /* synthesis syn_black_box */ ;

/* synthesis syn_props=""IP_Version = Ver1_0"" */
/* exemplar attribute ddrct_gen_e2_1_001 IP_Version Ver1_0 */

//////////////////////////////////////////////////////////////////////////////
//clock and reset inputs
input                                 clk;
input                                 rst_n;

input   [3:0]                         fb_cmd;
input   [`ADDR_WIDTH -1:0]            fb_addr;
input                                 fb_cmd_valid;
input                                 fb_init_start;
input   [4:0]                         fb_burst_length;
input   [`DSIZE-1:0]                  fb_write_data;
input   [`USER_DM-1:0]                fb_data_mask;
input   [1:0]                         data_valid_tap;  // DataValid delay


input   [4:0]                         tras;
input   [4:0]                         trc;
input   [2:0]                         trcd;
input   [2:0]                         trrd;
input   [4:0]                         trfc;
input   [2:0]                         trp; 
input   [2:0]                         tmrd;
input   [2:0]                         twr;  
input   [15:0]                        trefi;
input   [2:0]                         ar_burst_en;
`ifdef DDR2_MODE
    input   [1:0]                     trtp;
    input   [2:0]                     twtr;
    input   [6:0]                     tckp;
`else
    input                             ext_reg_en;
    input                             fb_burst_term;
`endif

output                                fb_cmd_rdy;
output                                init_done;
output                                fb_data_rdy;
output                                data_valid_tmp;    // data valid aligned
                                                         // to the rd command
                                                         // at the Memory I/F.
output  [2:0]                         cas_latency;


output                                ddr_cke;
output                                ddr_ras_n;
output                                ddr_cas_n;
output                                ddr_we_n;
output  [`CS_WIDTH-1:0]               ddr_cs_n;

`ifdef DDR2_MODE
    `ifdef CS_WIDTH_1
        output                        ddr_odt;
    `else
        output  [`CS_WIDTH -1 :0]     ddr_odt;
    `endif
`endif

output                                pio_read;
output                                dv_cs_csm_is_rd;   // cs is read 
output                                rd_cmd_pulse;      // RD cmd pulse 
output  [2:0]                         dv_bl_cycles;      // BL Cycle Count

output                                read_command;
output  [`ROW_WIDTH-1:0]              ddr_addr;
output  [1:0]                         ddr_ba;
output  [1:0]                         ddr_dqs_out;
output  [`DATA_WIDTH*2-1:0]           ddr_write_data;
output  [`USER_DM-1:0]                ddr_DM;
output                                ddr_write_valid;
output                                ddr_write_valid_early;

endmodule

///////////////////////////////////////////////////////////////////////////
