-- =============================================================================
--                           COPYRIGHT NOTICE
-- Copyright 2000-2002 (c) Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- This confidential and proprietary software may be used only as authorised by
-- a licensing agreement from Lattice Semiconductor Corporation.
-- The entire notice above must be reproduced on all authorized copies and
-- copies may only be made to the extent permitted by a licensing agreement from
-- Lattice Semiconductor Corporation.
--
-- Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
-- 5555 NE Moore Court                            408-826-6000 (other locations)
-- Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
-- U.S.A                                   email: techsupport@latticesemi.com
-- =============================================================================
--                         FILE DETAILS         
-- Project          : DDR Controller 
-- File             : pior_cell.vhd
-- Title            : pior_cell
-- Dependencies     : 
-- Description      : Tis module generate pio_read on different phases of clock 
-- =============================================================================
--                        REVISION HISTORY
-- Version          : 1.0
-- Mod. Date        : July 23, 2004
-- Changes Made     : Initial Creation
--
-- =============================================================================
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;
--library synplify;
--  use synplify.attributes.all;
  
entity pior_cell  is
   port(
     k_clk        	:in std_logic;
     kbar_clk      	:in std_logic;
     rst_n      	:in std_logic;
     sel_phase  	:in std_logic_vector(3 downto 0);
     pio_read_early 	:in std_logic;
     pio_read_dly  	:in std_logic;
     pio_read_out 	:out std_logic);
end pior_cell;     

architecture pior_cell_arch of pior_cell is
 
--signal pio_read_out	: std_logic;
signal pio_read_neg	: std_logic;
signal pio_read_kbpos	: std_logic;
signal pio_read_kneg	: std_logic;
signal pio_read_kbneg	: std_logic;
signal pio_read_kpos	: std_logic;

begin

process(k_clk, rst_n)
begin
	if (rst_n = '0') then
		pio_read_neg 	<= '0';
	elsif falling_edge(k_clk) then
		pio_read_neg	<= pio_read_early;
	end if;
end process;

process(kbar_clk, rst_n)
begin
	if (rst_n = '0') then
		pio_read_kbpos 	<= '0';
	elsif rising_edge(kbar_clk) then
		pio_read_kbpos	<= pio_read_neg;
	end if;
		
end process;

process(k_clk, rst_n)
begin
	if (rst_n = '0') then
		pio_read_kneg	<= '0';
	elsif falling_edge(k_clk) then
		pio_read_kneg	<= pio_read_dly;
	end if;
end process;

process(kbar_clk, rst_n)
begin
	if (rst_n = '0') then
		pio_read_kbneg 	<= '0';
	elsif falling_edge(kbar_clk) then
		pio_read_kbneg	<= pio_read_dly;
	end if;
end process;


process(k_clk, rst_n)
begin
	if (rst_n = '0') then
		pio_read_kpos	<= '0';
	elsif rising_edge(k_clk) then
		pio_read_kpos	<= pio_read_early;
	end if;
end process;


pio_read_out <= pio_read_kbpos when (sel_phase = "0001") else
                pio_read_kneg  when (sel_phase = "0010") else
                pio_read_kbneg when (sel_phase = "0100") else
                pio_read_kpos;
                
end pior_cell_arch;
