library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;

--library synplify;
-- use synplify.attributes.all;

entity ddr_data32_io is
   port (
	inddr_clk	: in std_logic_vector(3 downto 0);
	outddr_clk	: in std_logic;
	rst		: in std_logic;
	ddrclkpol	: in std_logic_vector(3 downto 0);
	ddr_write_data	: in std_logic_vector(63 downto 0);
	ddr_write_en	: in std_logic;
	ddr_read_data	: out std_logic_vector(63 downto 0);
	bidi		: inout std_logic_vector(31 downto 0));
end ddr_data32_io;

architecture ddr_data32_io_a of ddr_data32_io is

component bidi_byte_macro
  port(
     inddr_clk  :in std_logic;
     outddr_clk :in std_logic;
     rst        :in std_logic;
     ddrclkpol  :in std_logic;
     d_pos      :in std_logic_vector(7 downto 0);
     d_neg      :in std_logic_vector(7 downto 0);
     out_en     :in std_logic;
     q_pos      :out std_logic_vector(7 downto 0);
     q_neg      :out std_logic_vector(7 downto 0);
     bidi       :inout std_logic_vector(7 downto 0));
end component;

begin

U1_bidi_byte_macro : bidi_byte_macro
  port map(
	inddr_clk 	=> inddr_clk(0),
	outddr_clk	=> outddr_clk,
	rst		=> rst,
	ddrclkpol	=> ddrclkpol(0),
	d_neg		=> ddr_write_data(39 downto 32),
	d_pos		=> ddr_write_data(7 downto 0),
	out_en		=> ddr_write_en,
	q_pos		=> ddr_read_data(7 downto 0),
	q_neg		=> ddr_read_data(39 downto 32),
	bidi		=> bidi(7 downto 0));

U2_bidi_byte_macro : bidi_byte_macro
  port map(
	inddr_clk 	=> inddr_clk(1),
	outddr_clk	=> outddr_clk,
	rst		=> rst,
	ddrclkpol	=> ddrclkpol(1),
	d_neg		=> ddr_write_data(47 downto 40),
	d_pos		=> ddr_write_data(15 downto 8),
	out_en		=> ddr_write_en,
	q_pos		=> ddr_read_data(15 downto 8),
	q_neg		=> ddr_read_data(47 downto 40),
	bidi		=> bidi(15 downto 8));

U3_bidi_byte_macro : bidi_byte_macro
  port map(
	inddr_clk 	=> inddr_clk(2),
	outddr_clk	=> outddr_clk,
	rst		=> rst,
	ddrclkpol	=> ddrclkpol(2),
	d_neg		=> ddr_write_data(55 downto 48),
	d_pos		=> ddr_write_data(23 downto 16),
	out_en		=> ddr_write_en,
	q_pos		=> ddr_read_data(23 downto 16),
	q_neg		=> ddr_read_data(55 downto 48),
	bidi		=> bidi(23 downto 16));


U4_bidi_byte_macro : bidi_byte_macro
  port map(
	inddr_clk 	=> inddr_clk(3),
	outddr_clk	=> outddr_clk,
	rst		=> rst,
	ddrclkpol	=> ddrclkpol(3),
	d_neg		=> ddr_write_data(63 downto 56),
	d_pos		=> ddr_write_data(31 downto 24),
	out_en		=> ddr_write_en,
	q_pos		=> ddr_read_data(31 downto 24),
	q_neg		=> ddr_read_data(63 downto 56),
	bidi		=> bidi(31 downto 24));


end ddr_data32_io_a;













