library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;
--library synplify;
--  use synplify.attributes.all;
  
entity bidi_cell is
   port(
     inddr_clk  :in std_logic;
     outddr_clk :in std_logic;
     rst        :in std_logic;
     ddrclkpol  :in std_logic;
     d_pos      :in std_logic;
     d_neg      :in std_logic;
     out_en     :in std_logic;

     q_pos      :out std_logic;
     q_neg      :out std_logic;

     bidi       :inout std_logic);
end bidi_cell;     

architecture bidi_cell_arch of bidi_cell is
component ODDRXB
    GENERIC (REGSET : string := "RESET");
    port(
          DA		:	in	STD_ULOGIC;
          DB		:	in	STD_ULOGIC;
          CLK	        :	in	STD_ULOGIC;
          LSR	        :	in	STD_ULOGIC;
          Q		:	out	STD_ULOGIC
        );
end component;

component IDDRXB
    GENERIC (REGSET : string := "RESET");
    port(
          D		:	in	STD_ULOGIC;
          ECLK	        :	in	STD_ULOGIC;
          SCLK	        :	in	STD_ULOGIC;
          LSR		:	in	STD_ULOGIC;
          CE	        :	in	STD_ULOGIC;
          DDRCLKPOL     :	in	STD_ULOGIC;
          QA		:	out	STD_ULOGIC;
          QB		:	out	STD_ULOGIC
        );
end component;
        
component BB
    port(
          I		:	in	STD_ULOGIC;
          T		:	in	STD_ULOGIC;
          O		:	out	STD_ULOGIC;
          B		:	inout	STD_ULOGIC
        );
end component;

component TSALL
    port(

          TSALL		:	in	STD_ULOGIC
        );
end component;

signal  bb_to_in     : std_logic;
signal  out_to_bb    : std_logic;
signal  out_en_reg   : std_logic;
signal  bb_to_in_del : std_logic;
signal  rst_in       : std_logic;
signal  high         : std_logic;
signal  inv_outddr_clk : std_logic;
signal temp_out_en 	: std_logic;
signal temp_d_pos	: std_logic;
signal temp_d_neg	: std_logic;

--parameter DLY = 0.0;
begin

bb_to_in_del <= bb_to_in;
rst_in  <= rst; 
high <= '1';
inv_outddr_clk <= not outddr_clk;

temp_out_en <= out_en after 1 ns;

temp_d_pos <= d_pos after 1 ns;
temp_d_neg <= d_neg after 1 ns;

U1_IDDRXB : IDDRXB
    port map(
    D     => bb_to_in_del, 
    ECLK  => inddr_clk, 
    SCLK  => outddr_clk, 
    CE    => high,
    LSR   => rst_in, 
    DDRCLKPOL => ddrclkpol, 
    QA        =>q_pos, 
    QB        =>q_neg);

U1_ODDRXB : ODDRXB
   port map(
   DA   => temp_d_pos, 
   DB   => temp_d_neg, 
   LSR  => rst_in, 
   CLK  => inv_outddr_clk, 
   Q    => out_to_bb);

U1_TODDRXB : ODDRXB
   port map(
   DA   => temp_out_en, 
   DB   => temp_out_en, 
   LSR  => rst_in, 
   CLK  => inv_outddr_clk, 
   Q    => out_en_reg);


U1_BB : BB
   port map (
   I  => out_to_bb, 
   T  => out_en_reg, 
   O  => bb_to_in, 
   B  => bidi);

TSALL_INST :TSALL
   port map (
   TSALL => high);

end bidi_cell_arch;
