library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;
--library synplify;
--  use synplify.attributes.all;

entity ddr_dm32_io is
   port (
	clk	: in std_logic;
	rst	: in std_logic;
	data_in	: in std_logic_vector(7 downto 0);
	ddr_dataout : out std_logic_vector(3 downto 0));
end ddr_dm32_io;


architecture ddr_dm32_io_arch of ddr_dm32_io is

component ODDRXB
    GENERIC (REGSET : string := "RESET");
    port(
          DA		:	in	STD_ULOGIC;
          DB		:	in	STD_ULOGIC;
          CLK	        :	in	STD_ULOGIC;
          LSR	        :	in	STD_ULOGIC;
          Q		:	out	STD_ULOGIC
        );
end component;

begin

U1_ODDRXB : ODDRXB
   port map(
   DA   => data_in(4), 
   DB   => data_in(0), 
   LSR  => rst, 
   CLK  => clk, 
   Q    => ddr_dataout(0));

U2_ODDRXB : ODDRXB
   port map(
   DA   => data_in(5), 
   DB   => data_in(1), 
   LSR  => rst, 
   CLK  => clk, 
   Q    => ddr_dataout(1));

U3_ODDRXB : ODDRXB
   port map(
   DA   => data_in(6), 
   DB   => data_in(2), 
   LSR  => rst, 
   CLK  => clk, 
   Q    => ddr_dataout(2));

U4_ODDRXB : ODDRXB
   port map(
   DA   => data_in(7), 
   DB   => data_in(3), 
   LSR  => rst, 
   CLK  => clk, 
   Q    => ddr_dataout(3));


end ddr_dm32_io_arch;