`timescale 1ns/1ps
module bidi_byte_macro (
    inddr_clk,
    outddr_clk,
    rst,

    // Input signals to the INDDR module
    ddrclkpol,

    // Input signals to the OUTDDR module
    d_pos,
    d_neg,

    // Input signals to the BB module
    out_en,

    // Output signals from the INDDR module
    q_pos,
    q_neg,

    // Bi-directional signal from the BB module
    bidi
);

input                 inddr_clk;
input                 outddr_clk;
input                 rst;
input                 ddrclkpol;
input    [7:0]        d_pos;
input    [7:0]        d_neg;
input                 out_en;

output   [7:0]        q_pos;
output   [7:0]        q_neg;

inout    [7:0]        bidi;

//////////////// DQS Delay parameter  ///////////////////////////////
parameter DQS_DLY = 0 ;

// Pass the DQS_DLY into individual bidi_cell
defparam U1_bidi_cell.DQS_DLY = DQS_DLY;
defparam U2_bidi_cell.DQS_DLY = DQS_DLY;
defparam U3_bidi_cell.DQS_DLY = DQS_DLY;
defparam U4_bidi_cell.DQS_DLY = DQS_DLY;
defparam U5_bidi_cell.DQS_DLY = DQS_DLY;
defparam U6_bidi_cell.DQS_DLY = DQS_DLY;
defparam U7_bidi_cell.DQS_DLY = DQS_DLY;
defparam U8_bidi_cell.DQS_DLY = DQS_DLY;




// Instantiate the bi-directional cell
bidi_cell U1_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[0]), .d_neg(d_neg[0]), .out_en(out_en),
    .q_pos(q_pos[0]), .q_neg(q_neg[0]), .bidi(bidi[0])
);

bidi_cell U2_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[1]), .d_neg(d_neg[1]), .out_en(out_en),
    .q_pos(q_pos[1]), .q_neg(q_neg[1]), .bidi(bidi[1])
);

bidi_cell U3_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[2]), .d_neg(d_neg[2]), .out_en(out_en),
    .q_pos(q_pos[2]), .q_neg(q_neg[2]), .bidi(bidi[2])
);

bidi_cell U4_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[3]), .d_neg(d_neg[3]), .out_en(out_en),
    .q_pos(q_pos[3]), .q_neg(q_neg[3]), .bidi(bidi[3])
);

bidi_cell U5_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[4]), .d_neg(d_neg[4]), .out_en(out_en),
    .q_pos(q_pos[4]), .q_neg(q_neg[4]), .bidi(bidi[4])
);

bidi_cell U6_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[5]), .d_neg(d_neg[5]), .out_en(out_en),
    .q_pos(q_pos[5]), .q_neg(q_neg[5]), .bidi(bidi[5])
);

bidi_cell U7_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[6]), .d_neg(d_neg[6]), .out_en(out_en),
    .q_pos(q_pos[6]), .q_neg(q_neg[6]), .bidi(bidi[6])
);

bidi_cell U8_bidi_cell (
    .inddr_clk(inddr_clk), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol),
    .d_pos(d_pos[7]), .d_neg(d_neg[7]), .out_en(out_en),
    .q_pos(q_pos[7]), .q_neg(q_neg[7]), .bidi(bidi[7])
);

endmodule

