    PAR: Place And Route ispLever_v50_Production_Build (40).
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.
    Thu Jun 23 11:35:57 2005

    C:/ispTOOLS/ispfpga\bin\nt\par -f ddr_vhdl_pnr.p2t ddr_vhdl_pnr_map.ncd
    ddr_vhdl_pnr.dir ddr_vhdl_pnr.prf

    Preference file: ddr_vhdl_pnr.prf.

    Cost Table Summary
    Level/      Number      Timing      Run         NCD
    Cost [ncd]  Unrouted    Score       Time        Status
    ----------  --------    --------    -----       ------------
    5_1   *     0           0           01:19       Complete

    * : Design saved.

    par done!
    Lattice Place and Route Report for Design "ddr_vhdl_pnr_map.ncd"
    Thu Jun 23 11:35:57 2005

    Best Par Run
    PAR: Place And Route ispLever_v50_Production_Build (40).
    Command line: C:/ispTOOLS/ispfpga\bin\nt\par -f ddr_vhdl_pnr.p2t ddr_vhdl_pnr_map.ncd
    ddr_vhdl_pnr.dir ddr_vhdl_pnr.prf
    Preference file: ddr_vhdl_pnr.prf.
    Placement level-cost: 5-1.
    Routing Iterations: 6

    Loading design for application par from file ddr_vhdl_pnr_map.ncd.
       "ddr_top" is an NCD, version 3.0, vendor LATTICE, device LFXP10C,
    package FPBGA388, speed 5
    Loading device for application par from file 'mg5g36x40.nph' in environment
    C:/ispTOOLS/ispfpga.
    Package: Version 1.13.1.2, Status: PRODUCTION
    Speed Hardware Data: version 1.169

    Ignore Preference Error(s):  Yes
    Dumping design to file C:/DOCUME~1/jhsin/LOCALS~1/Temp/neo_43.
    Device utilization summary:

       PIO              113/280          40% used
                        113/244          46% bonded

       IOLOGIC           63/280          22% used
       DQS                2/16           12% used
       DQSDLL             1/2            50% used
       SLICE           1022/4864         21% used

       GSR                1/1           100% used
       PLL3               1/4            25% used

    Number of Signals: 2477
    Number of Connections: 6704
    The following 3 signals are selected to use the primary clock routing resources:
        pll_clk (driver: U1_ddr_sdram_mem_top/U1_kbar_clk_pll/U1_PLL, clk load #: 816)
        U1_ddr_sdram_mem_top/kbar_clk (driver: U1_ddr_sdram_mem_top/U1_kbar_clk_pll/U1_PLL, clk load #: 43)
        clk_in_c (driver: clk_in, clk load #: 14)

    The following 1 signal is selected to use the DCS clock routing resource:
        clk_in_c (driver: clk_in, clk load #: 14)

    The following 1 signal is selected to use the secondary clock routing resource:
        rst_n_c (driver: rst_n, clk load #: 0, sr load #: 664, ce load #: 0)

    WARNING - par: Secondary clock driver 'rst_n' is located at AB2 (not a
              dedicated clock PIO). Please check if user already located this
              comp, or this comp has dedicated connection with PLLs which must
              be placed at its corresponding dedicated PIOs.
    Signal rst_n_c is selected as Global Set/Reset.
    Starting Placer Phase 0.
    ................
    Finished Placer Phase 0.  REAL time: 4 secs

    Starting Placer Phase 1.
    Placer score = 558185.
    ...............................................
    ...............
    Placer score = 311256.
    Finished Placer Phase 1.  REAL time: 1 mins 2 secs

    Starting Placer Phase 2.
    .
    Placer score =  306127
    Finished Placer Phase 2.  REAL time: 1 mins 8 secs

    Total placer CPU time: 1 mins 8 secs

    Dumping design to file ddr_vhdl_pnr.dir/5_1.ncd.

    0 connections routed; 6706 unrouted.
    Starting router resource preassignment
    WARNING - par: The driver of secondary clock net rst_n_c is not placed on
              one of the PIO sites which are dedicated for secondary clocks.
              This secondary clock will be routed through general routing
              resource and may suffer from excessive delay or skew.
    Completed router resource preassignment. Real time: 1 mins 13 secs
    Starting iterative routing.

    For each routing iteration the number inside the parenthesis is the
    total time (in picoseconds) the design is failing the timing constraints.
    For each routing iteration the router will attempt to reduce this number
    until the number of routing iterations is completed or the value is 0
    meaning the design has fully met the timing constraints.

    End of iteration 1
    6706 successful; 0 unrouted; (0) real time: 1 mins 18 secs
    Dumping design to file ddr_vhdl_pnr.dir/5_1.ncd.
    Total CPU time 1 mins 17 secs
    Total REAL time: 1 mins 18 secs
    Completely routed.
    End of route.  6706 routed (100.00%); 0 unrouted.
    Checking DRC ...
    No errors found.
    Timing score: 0

    Total REAL time to completion: 1 mins 19 secs

    All signals are completely routed.

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.

    Generated from the file 'C:\EVALUATION BOARDS\XP\HIGH_END\EVAL_CODE\DDR\VHDL\PNR\ddr_vhdl_pnr.par'