// This module combines a wider databus to a narrower DDR bus.

module ddr_dm32_io (

    clk,
    rst,
    data_in,
    ddr_dataout
);

input                         clk;
input                         rst;
input  [7:0]                  data_in;
output [3:0]                  ddr_dataout;

wire   [3:0]                  ddr_dataout;

// Instantiate the OUTDDR modules to generate DDR data stream

ODDRXB U1_ODDRXB (.DB(data_in[4]), .DA(data_in[0]), .CLK(clk),
                  .LSR(rst), .Q(ddr_dataout[0]));

ODDRXB U2_ODDRXB (.DB(data_in[5]), .DA(data_in[1]), .CLK(clk),
                  .LSR(rst), .Q(ddr_dataout[1]));

ODDRXB U3_ODDRXB (.DB(data_in[6]), .DA(data_in[2]), .CLK(clk),
                  .LSR(rst), .Q(ddr_dataout[2]));

ODDRXB U4_ODDRXB (.DB(data_in[7]), .DA(data_in[3]), .CLK(clk),
                  .LSR(rst), .Q(ddr_dataout[3]));

endmodule
