library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;


entity ddr_pior32 is
   port (
	k_clk		: in std_logic;
	kbar_clk	: in std_logic;
	rst_n		: in std_logic;
	pio_read_dly	: in std_logic;
	pio_read_early	: in std_logic;
	sel_phase_0	: in std_logic_vector(3 downto 0);
	sel_phase_1	: in std_logic_vector(3 downto 0);
	sel_phase_2	: in std_logic_vector(3 downto 0);
	sel_phase_3	: in std_logic_vector(3 downto 0);
	pio_read_out	: out std_logic_vector(3 downto 0));
end ddr_pior32;

architecture ddr_pior32_arch of ddr_pior32 is
component pior_cell
   port(
     k_clk         	:in std_logic;
     kbar_clk      	:in std_logic;
     rst_n   	   	:in std_logic;
     sel_phase     	:in std_logic_vector(3 downto 0);
     pio_read_dly  	:in std_logic;
     pio_read_early 	:in std_logic;
     pio_read_out 	:out std_logic
);
end component; 

begin

U1_pior_cell : pior_cell
   port map(
		k_clk		=> k_clk,
		kbar_clk	=> kbar_clk,
		rst_n		=> rst_n,
		sel_phase	=> sel_phase_0,
		pio_read_early	=> pio_read_early,
		pio_read_dly	=> pio_read_dly,
		pio_read_out	=> pio_read_out(0));

U2_pior_cell : pior_cell
   port map(
		k_clk		=> k_clk,
		kbar_clk	=> kbar_clk,
		rst_n		=> rst_n,
		sel_phase	=> sel_phase_1,
		pio_read_early	=> pio_read_early,
		pio_read_dly	=> pio_read_dly,
		pio_read_out	=> pio_read_out(1));


U3_pior_cell : pior_cell
   port map(
		k_clk		=> k_clk,
		kbar_clk	=> kbar_clk,
		rst_n		=> rst_n,
		sel_phase	=> sel_phase_2,
		pio_read_early	=> pio_read_early,
		pio_read_dly	=> pio_read_dly,
		pio_read_out	=> pio_read_out(2));


U4_pior_cell : pior_cell
   port map(
		k_clk		=> k_clk,
		kbar_clk	=> kbar_clk,
		rst_n		=> rst_n,
		sel_phase	=> sel_phase_3,
		pio_read_early	=> pio_read_early,
		pio_read_dly	=> pio_read_dly,
		pio_read_out	=> pio_read_out(3));

end ddr_pior32_arch;