// This module instantiates the pior_cell for each of the dqs group.

module ddr_pior32 (

    rst_n,
    k_clk,
    kbar_clk,

    // Input signal from the core
    sel_phase_0,
    sel_phase_1,
    sel_phase_2,
    sel_phase_3,
    pio_read_dly,
    pio_read_early,

    // output signals to the core
    pio_read_out
);

//////////////////////////////////////////////////////////////////////////////
//clock and reset inputs
input                                 k_clk;
input                                 kbar_clk;
input                                 rst_n;
input                                 pio_read_dly;
input                                 pio_read_early;
input      [3:0]                      sel_phase_0;
input      [3:0]                      sel_phase_1;
input      [3:0]                      sel_phase_2;
input      [3:0]                      sel_phase_3;

// Output signals to the FPGA Logic
output     [3:0]                      pio_read_out;

//////////////////////////////////////////////////////////////////////////////
// Instintiate pior_cell
//////////////////////////////////////////////////////////////////////////////
pior_cell U1_pior_cell (
    .k_clk               (k_clk),
    .kbar_clk            (kbar_clk),
    .rst_n               (rst_n),
    .sel_phase           (sel_phase_0),
    .pio_read_early      (pio_read_early),
    .pio_read_dly        (pio_read_dly),
    .pio_read_out        (pio_read_out[0])
);

pior_cell U2_pior_cell (
    .k_clk               (k_clk),
    .kbar_clk            (kbar_clk),
    .rst_n               (rst_n),
    .sel_phase           (sel_phase_1),
    .pio_read_early      (pio_read_early),
    .pio_read_dly        (pio_read_dly),
    .pio_read_out        (pio_read_out[1])
);

pior_cell U3_pior_cell (
    .k_clk               (k_clk),
    .kbar_clk            (kbar_clk),
    .rst_n               (rst_n),
    .sel_phase           (sel_phase_2),
    .pio_read_early      (pio_read_early),
    .pio_read_dly        (pio_read_dly),
    .pio_read_out        (pio_read_out[2])
);

pior_cell U4_pior_cell (
    .k_clk               (k_clk),
    .kbar_clk            (kbar_clk),
    .rst_n               (rst_n),
    .sel_phase           (sel_phase_3),
    .pio_read_early      (pio_read_early),
    .pio_read_dly        (pio_read_dly),
    .pio_read_out        (pio_read_out[3])
);

endmodule
