library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;
--library synplify;
--  use synplify.attributes.all;
  
entity bidi_byte_macro is
   port(
     inddr_clk  :in std_logic;
     outddr_clk :in std_logic;
     rst        :in std_logic;
     ddrclkpol  :in std_logic;
     d_pos      :in std_logic_vector(7 downto 0);
     d_neg      :in std_logic_vector(7 downto 0);
     out_en     :in std_logic;

     q_pos      :out std_logic_vector(7 downto 0);
     q_neg      :out std_logic_vector(7 downto 0);

     bidi       :inout std_logic_vector(7 downto 0));
end bidi_byte_macro;  

architecture bidi_byte_macro_arch of bidi_byte_macro is
component bidi_cell 
   port(
     inddr_clk  :in std_logic;
     outddr_clk :in std_logic;
     rst        :in std_logic;
     ddrclkpol  :in std_logic;
     d_pos      :in std_logic;
     d_neg      :in std_logic;
     out_en     :in std_logic;

     q_pos      :out std_logic;
     q_neg      :out std_logic;

     bidi       :inout std_logic);
end component;     

begin

U1_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(0),
     d_neg      =>  d_neg(0),
     out_en     => out_en,
     q_pos      =>  q_pos(0),
     q_neg      =>  q_neg(0),
     bidi       =>   bidi(0));
    
U2_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(1),
     d_neg      =>  d_neg(1),
     out_en     => out_en,
     q_pos      =>  q_pos(1),
     q_neg      =>  q_neg(1),
     bidi       =>   bidi(1));

U3_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(2),
     d_neg      =>  d_neg(2),
     out_en     => out_en,
     q_pos      =>  q_pos(2),
     q_neg      =>  q_neg(2),
     bidi       =>   bidi(2));

U4_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(3),
     d_neg      =>  d_neg(3),
     out_en     => out_en,
     q_pos      =>  q_pos(3),
     q_neg      =>  q_neg(3),
     bidi       =>   bidi(3));

U5_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(4),
     d_neg      =>  d_neg(4),
     out_en     => out_en,
     q_pos      =>  q_pos(4),
     q_neg      =>  q_neg(4),
     bidi       =>   bidi(4));

U6_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(5),
     d_neg      =>  d_neg(5),
     out_en     => out_en,
     q_pos      =>  q_pos(5),
     q_neg      =>  q_neg(5),
     bidi       =>   bidi(5));

U7_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(6),
     d_neg      =>  d_neg(6),
     out_en     => out_en,
     q_pos      =>  q_pos(6),
     q_neg      =>  q_neg(6),
     bidi       =>   bidi(6));

U8_bidi_cell : bidi_cell
   port map(
     inddr_clk  => inddr_clk,
     outddr_clk => outddr_clk,
     rst        => rst,
     ddrclkpol  => ddrclkpol,
     d_pos      =>  d_pos(7),
     d_neg      =>  d_neg(7),
     out_en     => out_en,
     q_pos      =>  q_pos(7),
     q_neg      =>  q_neg(7),
     bidi       =>   bidi(7));

end bidi_byte_macro_arch;