    --------------------------------------------------------------------------------
    Lattice TRACE Report, Version ispLever_v50_SP1_Build (17)
    Thu Jun 23 11:12:39 2005

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.

    Report Information
    ------------------
    Command line:    trce -v 1 -o checkpnt.twr ddr_verilog_pnr.ncd ddr_verilog_pnr.prf
    Design file:     ddr_verilog_pnr.ncd
    Preference file: ddr_verilog_pnr.prf
    Device,speed:    LFXP10C,5
    Report level:    verbose report, limited to 1 item per preference
    --------------------------------------------------------------------------------

    Preference Summary

    FREQUENCY NET "pll_clk" 167.000000 MHz (0 errors)
                4096 items scored, 0 timing errors detected.
    Report:  168.634MHz is the maximum frequency for this preference.

    FREQUENCY NET "clk_in_c" 40.000000 MHz (0 errors)
                181 items scored, 0 timing errors detected.
    Report:  217.155MHz is the maximum frequency for this preference.

    BLOCK PATH FROM PORT "rst_n" (0 errors)
                64 items scored, 0 timing errors detected.

    BLOCK ASYNCPATHS
    BLOCK RESETPATHS
    --------------------------------------------------------------------------------

    ================================================================================
    Preference: FREQUENCY NET "pll_clk" 167.000000 MHz ;
                4096 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 0.058ns

     Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

       Source:         FF         Q              U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/row_addr_lat_4  (from pll_clk +)
       Destination:    FF         Data in        U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_row_1  (to pll_clk +)

       Delay:               5.750ns  (37.8% logic, 62.2% route), 6 logic levels.

     Constraint Details:

           5.750ns physical path delay SLICE_553 to SLICE_895 meets
           5.988ns delay constraint less
           0.000ns skew and
           0.180ns M_SET requirement (totaling 5.808ns) by 0.058ns

     Physical Path Details:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.342    R14C12B.CLK to     R14C12B.Q0 SLICE_553 (from pll_clk)
    ROUTE         1     1.657     R14C12B.Q0 to     R15C12C.A0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/row_addr_latZ0Z_4
    A0TOFCO_DE  ---     0.724     R15C12C.A0 to    R15C12C.FCO SLICE_34
    ROUTE         1     0.000    R15C12C.FCO to    R15C12D.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq5_4_n
    FCITOFCO_D  ---     0.103    R15C12D.FCI to    R15C12D.FCO SLICE_33
    ROUTE         1     0.000    R15C12D.FCO to    R15C13A.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq7_6_n
    FCITOFCO_D  ---     0.103    R15C13A.FCI to    R15C13A.FCO SLICE_32
    ROUTE         1     0.000    R15C13A.FCO to    R15C13B.FCI U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq9_8_n
    FCITOCOUT_  ---     0.603    R15C13B.FCI to   R15C13B.OFX1 SLICE_31
    ROUTE         1     1.123   R15C13B.OFX1 to     R15C19D.D0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/same_rowneq11_10_n
    CTOF_DEL    ---     0.300     R15C19D.D0 to     R15C19D.F0 SLICE_571
    ROUTE         2     0.795     R15C19D.F0 to     R16C19A.M0 U1_ddr_sdram_mem_top/U1_ddrct_gen_e2_1_001/U1_cdl/N_882_iZ0 (to pll_clk)
                      --------
                        5.750   (37.8% logic, 62.2% route), 6 logic levels.

     Clock Skew Details:

     Source Clock:
               Delay              Connection
              2.622ns PLL3_R27C1.CLKOP to R14C12B.CLK

     Destination Clock :
               Delay              Connection
              2.622ns PLL3_R27C1.CLKOP to R16C19A.CLK

    Report:  168.634MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: FREQUENCY NET "clk_in_c" 40.000000 MHz ;
                181 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

    Passed:  The following path meets requirements by 20.395ns

     Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

       Source:         FF         Q              wait_200us_count17_16_F2  (from M5GDCS20_clk_in_c +)
       Destination:    FF         Data in        waited_200us  (to M5GDCS20_clk_in_c +)

       Delay:               4.476ns  (27.7% logic, 72.3% route), 4 logic levels.

     Constraint Details:

           4.476ns physical path delay SLICE_57 to SLICE_845 meets
          25.000ns delay constraint less
           0.000ns skew and
           0.129ns DIN_SET requirement (totaling 24.871ns) by 20.395ns

     Physical Path Details:

       Name    Fanout   Delay (ns)          Site               Resource
    REG_DEL     ---     0.342    R31C11A.CLK to     R31C11A.Q1 SLICE_57 (from M5GDCS20_clk_in_c)
    ROUTE         2     1.668     R31C11A.Q1 to     R30C11A.B0 wait_200us_count_17
    CTOF_DEL    ---     0.300     R30C11A.B0 to     R30C11A.F0 SLICE_870
    ROUTE         1     0.518     R30C11A.F0 to     R30C11A.A1 G_2_0Z0Z_16
    CTOF_DEL    ---     0.300     R30C11A.A1 to     R30C11A.F1 SLICE_870
    ROUTE         1     1.048     R30C11A.F1 to      R30C9A.B0 G_2_0Z0Z_18
    CTOF_DEL    ---     0.300      R30C9A.B0 to      R30C9A.F0 SLICE_845
    ROUTE         1     0.000      R30C9A.F0 to     R30C9A.DI0 GZ0 (to M5GDCS20_clk_in_c)
                      --------
                        4.476   (27.7% logic, 72.3% route), 4 logic levels.

     Clock Skew Details:

     Source Clock:
               Delay              Connection
              0.460ns    LLDCS0.DCSOUT to R31C11A.CLK

     Destination Clock :
               Delay              Connection
              0.460ns    LLDCS0.DCSOUT to R30C9A.CLK

    Report:  217.155MHz is the maximum frequency for this preference.

    ================================================================================
    Preference: BLOCK PATH FROM PORT "rst_n" ;
                64 items scored, 0 timing errors detected.
    --------------------------------------------------------------------------------

     Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

       Source:         Port       Pad            rst_n
       Destination:    DQSDLL     Port           U1_ddr_sdram_mem_top/U1_DQSDLL  (to pll_clk +)

       Delay:               7.635ns  (11.4% logic, 88.6% route), 2 logic levels.

     Constraint Details:

           7.635ns physical path delay rst_n to U1_ddr_sdram_mem_top/U1_DQSDLL
           1.540ns RST_SET requirement

       Name    Fanout   Delay (ns)          Site               Resource
    PADI_DEL    ---     0.570        AB2.PAD to      AB2.PADDI rst_n
    ROUTE       666     5.731      AB2.PADDI to      R2C20C.C0 rst_n_c
    CTOF_DEL    ---     0.300      R2C20C.C0 to      R2C20C.F0 SLICE_990
    ROUTE         1     1.034      R2C20C.F0 to       TDLL.RST rst_n_c_iZ0 (to pll_clk)
                      --------
                        7.635   (11.4% logic, 88.6% route), 2 logic levels.

    Report Summary
    --------------
    ----------------------------------------------------------------------------
    Preference                              |   Constraint|       Actual|Levels
    ----------------------------------------------------------------------------
                                            |             |             |
    FREQUENCY NET "pll_clk" 167.000000 MHz  |             |             |
    ;                                       |  167.001 MHz|  168.634 MHz|     6
                                            |             |             |
    FREQUENCY NET "clk_in_c" 40.000000 MHz  |             |             |
    ;                                       |   40.000 MHz|  217.155 MHz|     4
                                            |             |             |
    BLOCK PATH FROM PORT "rst_n" ;          |            -|            -|     2
                                            |             |             |
    ----------------------------------------------------------------------------

    All preferences were met.

    Timing summary:

    Timing errors: 0  Score: 0

    Constraints cover 5649 paths, 3 nets, and 5627 connections (84.2% coverage)

    --------------------------------------------------------------------------------

    Generated from the file 'C:\EVALUATION BOARDS\XP\HIGH_END\EVAL_CODE\DDR\VERILOG\PNR\ddr_verilog_pnr.twr'