library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;

--library synplify;
--  use synplify.attributes.all;


entity kbar_clk_pll is
port(
	in_clk	: in std_logic;
	out_clk	: out std_logic;
	out_clk_p : out std_logic);
end kbar_clk_pll;

architecture kbar_clk_pll_a of kbar_clk_pll is

component EHXPLLB
	port(
		CLKI	: in std_logic;
		CLKFB	: in std_logic;
		RST	: in std_logic;
		DDAMODE	: in std_logic;
		DDAIZR	: in std_logic;
		DDAILAG	: in std_logic;
		DDAIDEL0 : in std_logic;
		DDAIDEL1 : in std_logic;
		DDAIDEL2 : in std_logic;
		CLKOP	: out std_logic;
		CLKOK	: out std_logic;
		CLKOS	: out std_logic;
		LOCK	: out std_logic;
		DDAOZR	: out std_logic;
		DDAOLAG	: out std_logic;
		DDAODEL0 : out std_logic;
		DDAODEL1 : out std_logic;
		DDAODEL2 : out std_logic);
end component;

attribute FIN 		: string;
attribute CLKI_DIV 	: string;
attribute CLKOP_DIV 	: string;
attribute CLKFB_DIV	: string;
attribute CLKOK_DIV	: string;
attribute DELAY_CNTL	: string;
attribute FDEL		: string;
attribute WAKE_ON_LOCK	: string;
attribute PHASEADJ	: string;
attribute DUTY		: string;

attribute FIN of U1_PLL 	: label is "33";
attribute CLKI_DIV of U1_PLL 	: label is "1";
attribute CLKOP_DIV of U1_PLL 	: label is "4";
attribute CLKFB_DIV of U1_PLL	: label is "5";
attribute CLKOK_DIV of U1_PLL	: label is "2";
attribute DELAY_CNTL of U1_PLL	: label is "STATIC";
attribute FDEL of U1_PLL	: label is "0";
attribute WAKE_ON_LOCK of U1_PLL : label is "OFF";
attribute PHASEADJ of U1_PLL	: label is "90";
attribute DUTY of U1_PLL	: label is "4";



signal out_clk_t : std_logic;

		
begin


U1_PLL : EHXPLLB
  port map (
		CLKI	=> in_clk,
		CLKFB	=> out_clk_t,
		RST	=> '0',
		DDAMODE	=> '0',
		DDAIZR	=> '1',
		DDAILAG	=> '0',
		DDAIDEL0 => '0',
		DDAIDEL1 => '0', 
		DDAIDEL2 => '0',
		CLKOP	=> out_clk_t,
		CLKOS	=> out_clk_p,
		CLKOK	=> open,
		LOCK	=> open,
		DDAOZR	=> open, 
		DDAOLAG	=> open,
		DDAODEL0 => open,
		DDAODEL1 => open,
		DDAODEL2 => open);

out_clk <= out_clk_t;
end kbar_clk_pll_a;