library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;

library EC;
  use EC.all;
--library synplify;
--  use synplify.attributes.all;
  
entity ddr_dqs32_io is
   port(
     rst      :in std_logic;
     dqs_clk  :in std_logic;
     core_clk :in std_logic;
     pio_read :in std_logic_vector(3 downto 0);
     tri_en   :in std_logic;
     dqsdel   :in std_logic;
     ddr_dqs_out :in std_logic_vector(1 downto 0);

     dqsout_pio  :out std_logic_vector(3 downto 0);
     dqsout_core :out std_logic_vector(3 downto 0);
     prmbdet     :out std_logic_vector(3 downto 0);
     ddrclkpol   :out std_logic_vector(3 downto 0);
     dqsi        :out std_logic_vector(3 downto 0);

     bidi       :inout std_logic_vector(3 downto 0));
end ddr_dqs32_io;     

architecture ddr_dqs32_iol_arch of ddr_dqs32_io is
component ODDRXB
    GENERIC (REGSET : string := "RESET");
    port(
          DA		:	in	STD_ULOGIC;
          DB		:	in	STD_ULOGIC;
          CLK	        :	in	STD_ULOGIC;
          LSR	        :	in	STD_ULOGIC;
          Q		:	out	STD_ULOGIC
        );
end component;
component BB
    port(
          I		:	in	STD_ULOGIC;
          T		:	in	STD_ULOGIC;
          O		:	out	STD_ULOGIC;
          B		:	inout	STD_ULOGIC
        );
end component;
component TSALL
    port(

          TSALL		:	in	STD_ULOGIC
        );
end component;
component DQSBUFB
    generic(DEL_ADJ          : string  := "PLUS";
            DEL_VAL          : string  := "0");
    port(
          DQSI		:	in	STD_ULOGIC;
          CLK		:	in	STD_ULOGIC;
          READ	        :	in	STD_ULOGIC;
          DQSDEL        :	in	STD_ULOGIC;
          DQSO		:	out	STD_ULOGIC;
          DDRCLKPOL	:	out	STD_ULOGIC;
          DQSC		:	out	STD_ULOGIC;
          PRMBDET	:	out	STD_ULOGIC
        );
end component;
signal out_to_bb  : std_logic_vector(3 downto 0);
signal tri_en_reg : std_logic_vector(3 downto 0);
signal dqsi_del0  : std_logic;
signal dqsi_del1  : std_logic;
signal dqsi_del2  : std_logic;
signal dqsi_del3  : std_logic;
signal high       : std_logic;
signal dqsi_int   : std_logic_vector(3 downto 0);
begin
dqsi <= dqsi_int;
high <= '1';
U1_ODDRXB : ODDRXB
   port map(
   DA   => ddr_dqs_out(0), 
   DB   => ddr_dqs_out(1), 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => out_to_bb(0));
   
U2_ODDRXB : ODDRXB
   port map(
   DA   => ddr_dqs_out(0), 
   DB   => ddr_dqs_out(1), 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => out_to_bb(1));

U3_ODDRXB : ODDRXB
   port map(
   DA   => ddr_dqs_out(0), 
   DB   => ddr_dqs_out(1), 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => out_to_bb(2));

U4_ODDRXB : ODDRXB
   port map(
   DA   => ddr_dqs_out(0), 
   DB   => ddr_dqs_out(1), 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => out_to_bb(3));


U1_TODDRXB : ODDRXB
   port map(
   DA   => tri_en, 
   DB   => tri_en, 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => tri_en_reg(0));

U2_TODDRXB : ODDRXB
   port map(
   DA   => tri_en, 
   DB   => tri_en, 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => tri_en_reg(1));
   
U3_TODDRXB : ODDRXB
   port map(
   DA   => tri_en, 
   DB   => tri_en, 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => tri_en_reg(2));

U4_TODDRXB : ODDRXB
   port map(
   DA   => tri_en, 
   DB   => tri_en, 
   LSR  => rst, 
   CLK  => dqs_clk, 
   Q    => tri_en_reg(3));


-- Instantiate the DQSBUF modules
dqsi_del0 <= dqsi_int(0);
dqsi_del1 <= dqsi_int(1);
dqsi_del2 <= dqsi_int(2);
dqsi_del3 <= dqsi_int(3);


-- Instantiate the DQSBUF modules
U1_DQSBUFB : DQSBUFB
    port map(
          DQSI		=>     dqsi_del0,
          CLK		=> core_clk,
          READ	        =>    pio_read(0),
          DQSDEL        => dqsdel,
          DQSO		=>  dqsout_pio(0),
          DDRCLKPOL	=>   ddrclkpol(0),
          DQSC		=> dqsout_core(0),
          PRMBDET	=>     prmbdet(0));

U2_DQSBUFB : DQSBUFB
    port map(
          DQSI		=>     dqsi_del1,
          CLK		=> core_clk,    
          READ	        =>    pio_read(1),
          DQSDEL        => dqsdel,     
          DQSO		=>  dqsout_pio(1),
          DDRCLKPOL	=>   ddrclkpol(1),
          DQSC		=> dqsout_core(1),
          PRMBDET	=>     prmbdet(1));

U3_DQSBUFB : DQSBUFB
    port map(
          DQSI		=>     dqsi_del2,
          CLK		=> core_clk,    
          READ	        =>    pio_read(2),
          DQSDEL        => dqsdel,     
          DQSO		=>  dqsout_pio(2),
          DDRCLKPOL	=>   ddrclkpol(2),
          DQSC		=> dqsout_core(2),
          PRMBDET	=>     prmbdet(2));

U4_DQSBUFB : DQSBUFB
    port map(
          DQSI		=>     dqsi_del3,
          CLK		=> core_clk,    
          READ	        =>    pio_read(3),
          DQSDEL        => dqsdel,     
          DQSO		=>  dqsout_pio(3),
          DDRCLKPOL	=>   ddrclkpol(3),
          DQSC		=> dqsout_core(3),
          PRMBDET	=>     prmbdet(3));



-- Instantiate the BB modules
U1_BB : BB
   port map (
   I  =>  out_to_bb(0), 
   T  => tri_en_reg(0), 
   O  =>  dqsi_int(0), 
   B  =>       bidi(0));

U2_BB : BB
   port map (
   I  =>  out_to_bb(1), 
   T  => tri_en_reg(1), 
   O  =>   dqsi_int(1), 
   B  =>       bidi(1));

U3_BB : BB
   port map (
   I  =>  out_to_bb(2), 
   T  => tri_en_reg(2), 
   O  =>   dqsi_int(2), 
   B  =>       bidi(2));

U4_BB : BB
   port map (
   I  =>  out_to_bb(3), 
   T  => tri_en_reg(3), 
   O  =>   dqsi_int(3), 
   B  =>       bidi(3));

 

--TSALL_INST :TSALL
--   port map (
--   TSALL => high);

end ddr_dqs32_iol_arch;


