`timescale 1ns/1ps
module ddr_data32_io (
    inddr_clk,
    outddr_clk,
    rst,

    // Input signals from the DQS BUF
    ddrclkpol,

    // Write data input from the core
    ddr_write_data,
    ddr_write_en,

    // Output signals to the core
    ddr_read_data,

    // Bi-directional signal at the Memory interface
    bidi
);

input    [3:0]        inddr_clk;
input                 outddr_clk;
input                 rst;
input    [3:0]        ddrclkpol;
input    [63:0]       ddr_write_data;
input                 ddr_write_en;

output   [63:0]       ddr_read_data;

inout    [31:0]       bidi;

// Instantiate the bidi_byte_macro modules

bidi_byte_macro U1_bidi_byte_macro (
    .inddr_clk(inddr_clk[0]), .outddr_clk(outddr_clk), .rst(rst),
    .ddrclkpol(ddrclkpol[0]),
    .d_neg(ddr_write_data[39:32]), .d_pos(ddr_write_data[7:0]),
    .out_en(ddr_write_en),
    .q_pos(ddr_read_data[7:0]), .q_neg(ddr_read_data[39:32]),
    .bidi(bidi[7:0])
);

bidi_byte_macro U2_bidi_byte_macro (
    .inddr_clk(inddr_clk[1]), .outddr_clk(outddr_clk), .rst(rst),
    .ddrclkpol(ddrclkpol[1]),
    .d_neg(ddr_write_data[47:40]), .d_pos(ddr_write_data[15:8]),
    .out_en(ddr_write_en),
    .q_pos(ddr_read_data[15:8]), .q_neg(ddr_read_data[47:40]),
    .bidi(bidi[15:8])
);

bidi_byte_macro U3_bidi_byte_macro (
    .inddr_clk(inddr_clk[2]), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol[2]),
    .d_neg(ddr_write_data[55:48]), .d_pos(ddr_write_data[23:16]),
    .out_en(ddr_write_en), 
    .q_pos(ddr_read_data[23:16]), .q_neg(ddr_read_data[55:48]),
    .bidi(bidi[23:16])
);

bidi_byte_macro U4_bidi_byte_macro (
    .inddr_clk(inddr_clk[3]), .outddr_clk(outddr_clk), .rst(rst), 
    .ddrclkpol(ddrclkpol[3]),
    .d_neg(ddr_write_data[63:56]), .d_pos(ddr_write_data[31:24]),
    .out_en(ddr_write_en), 
    .q_pos(ddr_read_data[31:24]), .q_neg(ddr_read_data[63:56]),
    .bidi(bidi[31:24])
);

endmodule
