// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2004 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                        FILE DETAILS
// Project          : DDR SDRAM Controller
// File             : pior_cell.v
// Title            : Generate READ signal for the DQS Buffer
// Description      : Based on the board trace delays, this module selects the
//                    appropriate read signal to the dqs buffer.  Read signal is 
//                    generated on multile clock edges.
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Author           : Sreenidhi Raatni
// Mod. Date        : Jul 26, 2004
// Changes Made     : Initial Creation
//
// =============================================================================

module pior_cell (

    // Clock and reset
    k_clk,
    kbar_clk,
    rst_n,
    pio_read_dly,
    pio_read_early,
    sel_phase,

    // Output signals to the FPGA Logic
    pio_read_out               // delayed pio_read signal based on user inputs

);

//////////////////////////////////////////////////////////////////////////////
//clock and reset inputs
input                                 k_clk;
input                                 kbar_clk;
input                                 rst_n;
input                                 pio_read_dly;
input                                 pio_read_early;
input      [3:0]                      sel_phase;

// Output signals to the FPGA Logic
output                                pio_read_out;

///////////////////////////////////////////////////////////////////////////
// Generate pio_read on different phases of clock

reg                                   pio_read_out;
reg                                   pio_read_neg;
reg                                   pio_read_kbpos;
reg                                   pio_read_kneg;
reg                                   pio_read_kbneg;
reg                                   pio_read_kpos;
///////////////////////////////////////////////////////////////////////////
// Register on -ve edge of k_clk

always @ (negedge k_clk or negedge rst_n) begin
    if (!rst_n) begin
        pio_read_neg      <= 'd0;
    end 
    else begin
        pio_read_neg      <= pio_read_early;
    end
end

///////////////////////////////////////////////////////////////////////////
// Register on +ve edge of kbar_clk

always @ (posedge kbar_clk or negedge rst_n) begin
    if (!rst_n) begin
        pio_read_kbpos    <= 'd0;
    end 
    else begin
        pio_read_kbpos    <= pio_read_neg;
    end
end
///////////////////////////////////////////////////////////////////////////
// Register on -ve edge of k_clk

always @ (negedge k_clk or negedge rst_n) begin
    if (!rst_n) begin
        pio_read_kneg     <= 'd0;
    end 
    else begin
        pio_read_kneg     <= pio_read_dly;
    end
end

///////////////////////////////////////////////////////////////////////////
// Register on -ve edge of kbar_clk

always @ (negedge kbar_clk or negedge rst_n) begin
    if (!rst_n) begin
        pio_read_kbneg    <= 'd0;
    end 
    else begin
        pio_read_kbneg    <= pio_read_dly;
    end
end

///////////////////////////////////////////////////////////////////////////
// Register on +ve edge of k_clk

always @ (posedge k_clk or negedge rst_n) begin
    if (!rst_n) begin
        pio_read_kpos     <= 'd0;
    end 
    else begin
        pio_read_kpos     <= pio_read_early;
    end
end

///////////////////////////////////////////////////////////////////////////
// Generate pio_read on different phases of clock based on sel_phase
// sel_phase
// 0001 -- Selects KBAR Positive
// 0010 -- Selects K    Negitive
// 0100 -- Selects KBAR Negitive
// 1000 -- Selects K    Positive
///////////////////////////////////////////////////////////////////////////
always @ (sel_phase or pio_read_kbpos or pio_read_kneg or pio_read_kbneg or pio_read_kpos) begin
   case(sel_phase)
      4'b0001: pio_read_out  <= pio_read_kbpos;
      4'b0010: pio_read_out  <= pio_read_kneg;
      4'b0100: pio_read_out  <= pio_read_kbneg;
      default: pio_read_out  <= pio_read_kpos;
   endcase
end

///////////////////////////////////////////////////////////////////////////
endmodule
