`timescale 1ns/1ps
module bidi_cell (

    inddr_clk,
    outddr_clk,
    rst,

    // Input signals to the INDDR module
    ddrclkpol,

    // Input signals to the OUTDDR module
    d_pos,
    d_neg,

    // Input signals to the BB module
    out_en,

    // Output signals from the INDDR module
    q_pos,
    q_neg,

    // Bi-directional signal from the BB module
    bidi
);

input                 inddr_clk;
input                 outddr_clk;
input                 rst;
input                 ddrclkpol;
input                 d_pos;
input                 d_neg;
input                 out_en;

output                q_pos;
output                q_neg;

inout                 bidi;

// Interconnecting wires

wire                  bb_to_in;
wire                  bb_to_in_tmp;
wire                  out_to_bb;
wire                  out_en_reg;

// Instantiate the IDDRXB, ODDRXB and BB modules

IDDRXB U1_IDDRXB (.D(bb_to_in), .ECLK(inddr_clk), .SCLK(outddr_clk), .CE(1'b1),
                  .LSR(rst), .DDRCLKPOL(ddrclkpol), .QA(q_pos), .QB(q_neg));

ODDRXB U1_ODDRXB (.DA(d_pos), .DB(d_neg), .LSR(rst), .CLK(~outddr_clk), 
                  .Q(out_to_bb));

ODDRXB U1_TODDRXB (.DA(out_en), .DB(out_en), .LSR(rst), .CLK(~outddr_clk),
                   .Q(out_en_reg));

////////////// Parameter for the DQS delay  /////////////////////////
parameter DQS_DLY = 0 ;

assign #DQS_DLY bb_to_in = bb_to_in_tmp;


BB U1_BB (.I(out_to_bb), .T(out_en_reg), .O(bb_to_in_tmp), .B(bidi));

//TSALL TSALL_INST (.TSALL(1'b1));

endmodule
