    PAR: Place And Route ispLever_v50_Production_Build (40).
    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.
    Wed Jun 29 12:44:38 2005

    C:/ispTOOLS/ispfpga\bin\nt\par -f fcram_verilog_pnr.p2t
    fcram_verilog_pnr_map.ncd fcram_verilog_pnr.dir fcram_verilog_pnr.prf

    Preference file: fcram_verilog_pnr.prf.

    Cost Table Summary
    Level/      Number      Timing      Run         NCD
    Cost [ncd]  Unrouted    Score       Time        Status
    ----------  --------    --------    -----       ------------
    5_72  *     0           283         01:28       Complete
    5_12        0           789         01:21       Complete
    5_54        0           802         01:26       Complete
    5_91        0           961         01:27       Complete
    5_29        0           1011        01:09       Complete
    5_62        0           1153        01:28       Complete
    5_3         0           1163        01:20       Complete
    5_41        0           1211        01:17       Complete
    5_48        0           1257        01:35       Complete
    5_22        0           1261        01:12       Complete
    5_1         0           1304        01:15       Complete
    5_14        0           1316        01:20       Complete
    5_5         0           1409        01:09       Complete
    5_25        0           1441        01:18       Complete
    5_34        0           1459        01:19       Complete
    5_13        0           1505        01:32       Complete
    5_37        0           1726        01:22       Complete
    5_71        0           1747        01:17       Complete
    5_53        0           1766        01:25       Complete
    5_6         0           1798        01:17       Complete
    5_77        0           1798        01:31       Complete
    5_16        0           1832        01:09       Complete
    5_84        0           1882        01:24       Complete
    5_21        0           1937        01:10       Complete
    5_76        0           2046        01:10       Complete
    5_32        0           2136        01:19       Complete
    5_7         0           2159        01:02       Complete
    5_99        0           2167        01:28       Complete
    5_23        0           2245        01:19       Complete
    5_40        0           2343        01:24       Complete
    5_92        0           2351        01:31       Complete
    5_18        0           2366        01:16       Complete
    5_26        0           2367        01:16       Complete
    5_45        0           2368        01:30       Complete
    5_65        0           2392        01:22       Complete
    5_19        0           2526        01:04       Complete
    5_60        0           2547        01:22       Complete
    5_31        0           2567        01:35       Complete
    5_30        0           2577        01:17       Complete
    5_47        0           2602        01:19       Complete
    5_67        0           2614        01:22       Complete
    5_52        0           2635        01:24       Complete
    5_100       0           2663        01:30       Complete
    5_58        0           2692        01:20       Complete
    5_97        0           2699        01:35       Complete
    5_2         0           2711        01:20       Complete
    5_69        0           2726        01:51       Complete
    5_75        0           2755        01:14       Complete
    5_83        0           2772        01:27       Complete
    5_79        0           2810        01:15       Complete
    5_82        0           2853        01:33       Complete
    5_10        0           2855        01:13       Complete
    5_57        0           2901        01:21       Complete
    5_28        0           2964        01:13       Complete
    5_89        0           2971        01:31       Complete
    5_20        0           3040        01:11       Complete
    5_49        0           3122        01:11       Complete
    5_8         0           3172        01:13       Complete
    5_35        0           3188        01:16       Complete
    5_39        0           3226        01:19       Complete
    5_51        0           3294        01:24       Complete
    5_61        0           3307        01:26       Complete
    5_68        0           3310        01:24       Complete
    5_17        0           3441        01:19       Complete
    5_74        0           3445        01:31       Complete
    5_87        0           3446        01:23       Complete
    5_36        0           3473        02:00       Complete
    5_27        0           3515        01:13       Complete
    5_90        0           3540        01:35       Complete
    5_93        0           3594        01:22       Complete
    5_50        0           3616        01:11       Complete
    5_63        0           3647        01:23       Complete
    5_78        0           3698        01:32       Complete
    5_15        0           3749        01:06       Complete
    5_38        0           3774        01:24       Complete
    5_98        0           3804        01:31       Complete
    5_81        0           3928        01:34       Complete
    5_9         0           4053        01:15       Complete
    5_64        0           4056        01:33       Complete
    5_95        0           4119        01:18       Complete
    5_46        0           4183        01:16       Complete
    5_24        0           4238        01:26       Complete
    5_56        0           4336        01:19       Complete
    5_43        0           4462        01:39       Complete
    5_59        0           4624        01:39       Complete
    5_33        0           4692        01:17       Complete
    5_96        0           4833        01:41       Complete
    5_94        0           4878        01:59       Complete
    5_80        0           4916        01:41       Complete
    5_86        0           4937        01:24       Complete
    5_66        0           5124        01:20       Complete
    5_11        0           5310        01:15       Complete
    5_88        0           5435        01:22       Complete
    5_42        0           5481        01:27       Complete
    5_55        0           5692        01:23       Complete
    5_44        0           5724        01:40       Complete
    5_4         0           6273        01:18       Complete
    5_70        0           7333        01:33       Complete
    5_73        0           10025       01:55       Complete
    5_85        0           11147       01:57       Complete

    * : Design saved.

    par done!
    Lattice Place and Route Report for Design "fcram_verilog_pnr_map.ncd"
    Wed Jun 29 14:20:49 2005

    Best Par Run
    PAR: Place And Route ispLever_v50_Production_Build (40).
    Command line: C:/ispTOOLS/ispfpga\bin\nt\par -f fcram_verilog_pnr.p2t
    fcram_verilog_pnr_map.ncd fcram_verilog_pnr.dir fcram_verilog_pnr.prf
    Preference file: fcram_verilog_pnr.prf.
    Placement level-cost: 5-72.
    Routing Iterations: 6

    Loading design for application par from file
    C:/DOCUME~1/jhsin/LOCALS~1/Temp/neo_58.
       "fcram_test_top" is an NCD, version 3.0, vendor LATTICE, device LFEC20E,
    package FPBGA672, speed 5
    Package: Version 1.8, Status: PRODUCTION
    Speed Hardware Data: version 1.121
    Device utilization summary:

       PIO               97/400          24% used
                         97/400          24% bonded

       IOLOGIC           31/400           7% used
       DQS                1/24            4% used
       DQSDLL             1/2            50% used
       SLICE            560/9856          5% used

       GSR                1/1           100% used
       PLL3               1/4            25% used

    Number of Signals: 1298
    Number of Connections: 3494
    The following 3 signals are selected to use the primary clock routing resources:
        pll_clk (driver: U1_fcram_top/sys_clk_pll/ehxpllb_5, clk load #: 331)
        U1_fcram_top/sys_clk_0 (driver: U1_fcram_top/sys_clk_pll/ehxpllb_5, clk load #: 29)
        clk_in_c (driver: clk_in, clk load #: 19)

    The following 1 signal is selected to use the DCS clock routing resource:
        clk_in_c (driver: clk_in, clk load #: 19)

    WARNING - par: Primary clock driver 'clk_in' is located at F6 (not a
              dedicated clock PIO). Please check if user already located this
              comp, or this comp has dedicated connection with PLLs which must
              be placed at its corresponding dedicated PIOs.
    The following 1 signal is selected to use the secondary clock routing resource:
        rst_n_c (driver: rst_n, clk load #: 0, sr load #: 138, ce load #: 12)

    WARNING - par: Secondary clock driver 'rst_n' is located at K1 (not a
              dedicated clock PIO). Please check if user already located this
              comp, or this comp has dedicated connection with PLLs which must
              be placed at its corresponding dedicated PIOs.
    Signal rst_n_c is selected as Global Set/Reset.
    Starting Placer Phase 0.
    ..............
    Finished Placer Phase 0.  REAL time: 9 secs

    Starting Placer Phase 1.
    Placer score = 1770483.
    ..................................
    Placer score = 1628522.
    Finished Placer Phase 1.  REAL time: 55 secs

    Starting Placer Phase 2.
    .
    Placer score =  1612700
    Finished Placer Phase 2.  REAL time: 1 mins 1 secs

    Total placer CPU time: 58 secs

    Dumping design to file fcram_verilog_pnr.dir/5_72.ncd.

    0 connections routed; 3495 unrouted.
    Starting router resource preassignment
    WARNING - par: The driver of dcs clock net clk_in_c is not placed on one of
              the PIO sites which are dedicated for primary clocks.  This dcs
              clock will be routed through general routing resource and may
              suffer from excessive delay or skew.
    WARNING - par: The driver of secondary clock net rst_n_c is not placed on
              one of the PIO sites which are dedicated for secondary clocks.
              This secondary clock will be routed through general routing
              resource and may suffer from excessive delay or skew.
    Completed router resource preassignment. Real time: 1 mins 13 secs
    Starting iterative routing.

    For each routing iteration the number inside the parenthesis is the
    total time (in picoseconds) the design is failing the timing constraints.
    For each routing iteration the router will attempt to reduce this number
    until the number of routing iterations is completed or the value is 0
    meaning the design has fully met the timing constraints.

    End of iteration 1
    3495 successful; 0 unrouted; (2279) real time: 1 mins 20 secs
    Dumping design to file fcram_verilog_pnr.dir/5_72.ncd.
    End of iteration 2
    3495 successful; 0 unrouted; (283) real time: 1 mins 21 secs
    Dumping design to file fcram_verilog_pnr.dir/5_72.ncd.
    End of iteration 3
    3495 successful; 0 unrouted; (283) real time: 1 mins 22 secs
    End of iteration 4
    3495 successful; 0 unrouted; (283) real time: 1 mins 24 secs
    End of iteration 5
    3495 successful; 0 unrouted; (283) real time: 1 mins 25 secs
    End of iteration 6
    3495 successful; 0 unrouted; (283) real time: 1 mins 27 secs
    Giving up.
    Total CPU time 1 mins 17 secs
    Total REAL time: 1 mins 27 secs
    Completely routed.
    End of route.  3495 routed (100.00%); 0 unrouted.
    Checking DRC ...
    No errors found.
    Timing score: 283

    Total REAL time to completion: 1 mins 28 secs

    All signals are completely routed.

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2005 Lattice Semiconductor Corporation,  All rights reserved.

    Generated from the file 'C:\EVALUATION BOARDS\EC\HIGH_END\EVAL_CODE\FCRAM\VERILOG\PNR\fcram_verilog_pnr.par'