
########## Tcl recorder starts at 06/28/05 13:53:20 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/edfin\" -i ../syn/rev_1/fcram_test_top.edn -jhd fcram_test_top.jhd -log fcram_test_top.log -dev orca -lbp \"$fpga_dir/data\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/28/05 13:53:20 ###########


########## Tcl recorder starts at 06/28/05 13:53:54 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$fpga_bin/edif2ngd\" -l ep5g00 -d lfec20e \"../syn/rev_1/fcram_test_top.edn\" \"fcram_test_top.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edif2ngd\" -l ep5g00 -d lfec20e \"../syn/rev_1/fcram_test_top.edn\" \"fcram_test_top.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/edfmodgen\" -inp \"../syn/rev_1/fcram_test_top.edn\" -log \"fcram_test_top.emg\" -arch ep5g00 -dev lfec20e"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"fcram_verilog_pnr.tcy\" -w \"fcram_test_top.ngo\" -m \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a ep5g00 -d lfec20e -p \"$proj_dir\" \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/28/05 13:53:54 ###########


########## Tcl recorder starts at 06/28/05 14:00:25 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# HTML Place & Route Report
if [catch {open fcram_verilog_pnr.rsp w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.rsp: $rspFile"
} else {
	puts $rspFile "-mrp fcram_verilog_pnr.mrp
-pad fcram_verilog_pnr.pad
-par fcram_verilog_pnr.par
-ptwr fcram_verilog_pnr.twr
fcram_verilog_pnr
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/htmlrpt\" -f \"fcram_verilog_pnr.rsp\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.rsp

########## Tcl recorder end at 06/28/05 14:00:25 ###########


########## Tcl recorder starts at 06/28/05 14:02:49 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/edfin\" -i ../syn/rev_1/fcram_test_top.edn -jhd fcram_test_top.jhd -log fcram_test_top.log -dev orca -lbp \"$fpga_dir/data\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/28/05 14:02:49 ###########


########## Tcl recorder starts at 06/28/05 14:02:49 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$fpga_bin/edif2ngd\" -l ep5g00 -d lfec20e \"../syn/rev_1/fcram_test_top.edn\" \"fcram_test_top.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edif2ngd\" -l ep5g00 -d lfec20e \"../syn/rev_1/fcram_test_top.edn\" \"fcram_test_top.ngo\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/edfmodgen\" -inp \"../syn/rev_1/fcram_test_top.edn\" -log \"fcram_test_top.emg\" -arch ep5g00 -dev lfec20e"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"fcram_verilog_pnr.tcy\" -w \"fcram_test_top.ngo\" -m \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a ep5g00 -d lfec20e -p \"$proj_dir\" \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/28/05 14:02:49 ###########


########## Tcl recorder starts at 06/28/05 15:31:45 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$cpld_bin/edfmodgen\" -inp \"../syn/rev_1/fcram_test_top.edn\" -log \"fcram_test_top.emg\" -arch ep5g00 -dev lfec20e"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"fcram_verilog_pnr.tcy\" -w \"fcram_test_top.ngo\" -m \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a ep5g00 -d lfec20e -p \"$proj_dir\" \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/28/05 15:31:45 ###########


########## Tcl recorder starts at 06/28/05 17:47:34 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# HTML Place & Route Report
if [catch {open fcram_verilog_pnr.rsp w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.rsp: $rspFile"
} else {
	puts $rspFile "-mrp fcram_verilog_pnr.mrp
-pad fcram_verilog_pnr.pad
-par fcram_verilog_pnr.par
-ptwr fcram_verilog_pnr.twr
fcram_verilog_pnr
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/htmlrpt\" -f \"fcram_verilog_pnr.rsp\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.rsp

########## Tcl recorder end at 06/28/05 17:47:34 ###########


########## Tcl recorder starts at 06/28/05 17:58:39 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$cpld_bin/edfmodgen\" -inp \"../syn/rev_1/fcram_test_top.edn\" -log \"fcram_test_top.emg\" -arch ep5g00 -dev lfec20e"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"fcram_verilog_pnr.tcy\" -w \"fcram_test_top.ngo\" -m \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a ep5g00 -d lfec20e -p \"$proj_dir\" \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\" -c 20"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/28/05 17:58:39 ###########


########## Tcl recorder starts at 06/29/05 09:05:22 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# HTML Place & Route Report
if [catch {open fcram_verilog_pnr.rsp w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.rsp: $rspFile"
} else {
	puts $rspFile "-mrp fcram_verilog_pnr.mrp
-pad fcram_verilog_pnr.pad
-par fcram_verilog_pnr.par
-ptwr fcram_verilog_pnr.twr
fcram_verilog_pnr
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/htmlrpt\" -f \"fcram_verilog_pnr.rsp\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.rsp

########## Tcl recorder end at 06/29/05 09:05:22 ###########


########## Tcl recorder starts at 06/29/05 09:09:11 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\" -c 40"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/29/05 09:09:11 ###########


########## Tcl recorder starts at 06/29/05 10:19:52 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$cpld_bin/edfmodgen\" -inp \"../syn/rev_1/fcram_test_top.edn\" -log \"fcram_test_top.emg\" -arch ep5g00 -dev lfec20e"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"fcram_verilog_pnr.tcy\" -w \"fcram_test_top.ngo\" -m \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a ep5g00 -d lfec20e -p \"$proj_dir\" \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\" -c 40"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/29/05 10:19:52 ###########


########## Tcl recorder starts at 06/29/05 12:32:53 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# HTML Place & Route Report
if [catch {open fcram_verilog_pnr.rsp w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.rsp: $rspFile"
} else {
	puts $rspFile "-mrp fcram_verilog_pnr.mrp
-pad fcram_verilog_pnr.pad
-par fcram_verilog_pnr.par
-ptwr fcram_verilog_pnr.twr
fcram_verilog_pnr
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/htmlrpt\" -f \"fcram_verilog_pnr.rsp\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.rsp

########## Tcl recorder end at 06/29/05 12:32:53 ###########


########## Tcl recorder starts at 06/29/05 12:44:14 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Generate Bitstream Data
if [runCmd "\"$cpld_bin/edfmodgen\" -inp \"../syn/rev_1/fcram_test_top.edn\" -log \"fcram_test_top.emg\" -arch ep5g00 -dev lfec20e"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"fcram_verilog_pnr.tcy\" -w \"fcram_test_top.ngo\" -m \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngx\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a ep5g00 -d lfec20e -p \"$proj_dir\" \"fcram_test_top.ngo\" \"fcram_verilog_pnr.ngd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$fpga_bin/map\" -a ep5g00 -p lfec20e -t fpbga672 -s 5 \"fcram_verilog_pnr.ngd\" -o \"fcram_verilog_pnr_map.ncd\" -mp \"fcram_verilog_pnr.mrp\" \"fcram_verilog_pnr.prf\" -c 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.mt
-to fcram_verilog_pnr.tw1
-o fcram_verilog_pnr.tcm
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.mrp
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"fcram_verilog_pnr.cmm\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr_map.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.p2t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p2t: $rspFile"
} else {
	puts $rspFile "-w
-i 6
-l 5
-n 0
-t 1
-s 1
-c 0
-e 0
"
	close $rspFile
}
if [catch {open fcram_verilog_pnr.p3t w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.p3t: $rspFile"
} else {
	puts $rspFile "-rem
-log fcram_verilog_pnr.log
-o fcram_verilog_pnr.par
-pr fcram_verilog_pnr.prf
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p fcram_verilog_pnr.p2t -f \"fcram_verilog_pnr.p3t\" \"fcram_verilog_pnr_map.ncd\" \"fcram_verilog_pnr.ncd\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [catch {open fcram_verilog_pnr.cm2 w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.cm2: $rspFile"
} else {
	puts $rspFile "-t fcram_verilog_pnr.pt
-to fcram_verilog_pnr.twr
-o fcram_verilog_pnr.tcp
-log fcram_verilog_pnr.log
-pr fcram_verilog_pnr.prf
-rpt fcram_verilog_pnr.par
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"fcram_verilog_pnr.cmp\" -f \"fcram_verilog_pnr.cm2\" -arch ep5g00 \"fcram_verilog_pnr.ncd\" -l 60"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.cm2
if [catch {open fcram_verilog_pnr.t2b w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.t2b: $rspFile"
} else {
	puts $rspFile "-g CfgMode:Disable
-g readback:sram
-g ramcfg:reset
-g synsrc:no
-g pllset:none
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"fcram_verilog_pnr.t2b\" -w \"fcram_verilog_pnr.ncd\" \"fcram_verilog_pnr.prf\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 06/29/05 12:44:14 ###########


########## Tcl recorder starts at 06/29/05 15:07:35 ##########

set version "5.0"
set proj_dir "C:/evaluation boards/ec/high_end/eval_code/fcram/verilog/pnr"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]

switch $tcl_platform(platform) {
   windows {
      set fpga_bin [file join $fpga_dir "bin" "nt"]
	     if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
	        set env(PATH) "$fpga_bin;$env(PATH)" } }
   unix {
      set fpga_bin [file join $fpga_dir "bin" "sol"]
      if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
         set env(PATH) "$fpga_bin;$env(PATH)"}}}

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# HTML Place & Route Report
if [catch {open fcram_verilog_pnr.rsp w} rspFile] {
	puts stderr "Cannot create response file fcram_verilog_pnr.rsp: $rspFile"
} else {
	puts $rspFile "-mrp fcram_verilog_pnr.mrp
-pad fcram_verilog_pnr.pad
-par fcram_verilog_pnr.par
-ptwr fcram_verilog_pnr.twr
fcram_verilog_pnr
"
	close $rspFile
}
if [runCmd "\"$fpga_bin/htmlrpt\" -f \"fcram_verilog_pnr.rsp\""] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
file delete fcram_verilog_pnr.rsp

########## Tcl recorder end at 06/29/05 15:07:35 ###########

