
/*
 * This PLL is used to support the FCRAM controller.
 *
 * This version of the ehpll was captured by hand rather than the
 * GUI based logic builder.
 */


`timescale 1 ns / 100 ps
module fcram_ehxpllb (pll_rst, clk_in, pll_fbk, clkop, clkos, pll_lock, clkok);

    input clk_in;
    input pll_fbk;
    input pll_rst;

    output clkop;
    output clkos;
    output clkok;
    output pll_lock;

     /*
     * FIN 		= "33";	// Input frequency (ref_clk)
     * CLKI_DIV 	= "1";		// Reference clock  divider (1-256)
     * CLKFB_DIV 	= "5";		// Feed-back clock divider (1-128)
     * CLKOP_DIV 	= "4";		// Primary clock output divider (2-128)
     * CLKOK_DIV 	= "2";		// Clock OK divider (2-128)
     * DELAY_CNTL 	= "STATIC";	// STATIC (fuse settings) DYNAMIC (external inputs below)
     * FDEL 		= "0";		// Lead(neg)/Lag(pos): "0" results in clkop leading ref by 0ps
     * WAKE_ON_LOCK 	= "ON";		// ??
     * PHASEADJ 	= "270";		// CLKOS Phase shift 0, 45, 90, ... 315 degrees
     * DUTY 		= "4";		// Play around here, decription is confusing
     * LOCK_CYC 	= "16";		// cycles before lock decalred
     */


    // synopsys translate_off
    defparam ehxpllb_5.FIN 		= "33";	/* Input frequency (ref_clk) */
    defparam ehxpllb_5.CLKI_DIV 	= "1";		/* Reference clock  divider (1-256) */
    defparam ehxpllb_5.CLKFB_DIV 	= "5";		/* Feed-back clock divider (1-128) */
    defparam ehxpllb_5.CLKOP_DIV 	= "4";		/* Primary clock output divider (2-128) */
    defparam ehxpllb_5.CLKOK_DIV 	= "2";		/* Clock OK divider (2-128) */
    defparam ehxpllb_5.DELAY_CNTL 	= "STATIC";	/* STATIC (fuse settings) DYNAMIC (external inputs below) */
    defparam ehxpllb_5.FDEL 		= "0";		/* Lead(neg)/Lag(pos): "0" results in clkop in phase with input clock */
    defparam ehxpllb_5.WAKE_ON_LOCK 	= "ON";		/* ?? */
    defparam ehxpllb_5.PHASEADJ 	= "270";	/* CLKOS Phase shift 0, 45, 90, ... 315 degrees */
    defparam ehxpllb_5.DUTY 		= "4";		/* Play around here, decription is confusing */
    defparam ehxpllb_5.LOCK_CYC 	= "16";		/* cycles before lock decalred */
    // synopsys translate_on

    EHXPLLB ehxpllb_5 (

	.RST		(pll_rst), 
	.CLKI		(clk_in), 
	.CLKFB		(pll_fbk), 
	.DDAMODE	(1'b0),		// Mode control, Set up for static settings for now 
	.DDAIZR		(1'b0), 
	.DDAILAG	(1'b0), 
	.DDAIDEL0	(1'b0), 
	.DDAIDEL1	(1'b0), 
	.DDAIDEL2	(1'b0), 

	.CLKOP		(clkop),	// Primary 350Mhz clock
 	.CLKOS		(clkos), 	// Primary 350Mhz phase shifted
 	.CLKOK		(clkok), 	// Secondary 1/4 freq non-phase shift
 	.LOCK		(pll_lock),
 	.DDAOZR		(), 
 	.DDAOLAG	(), 
 	.DDAODEL0	(), 
 	.DDAODEL1	(), 
 	.DDAODEL2	()
    )

    /* synthesis FIN 		= "33" */
    /* synthesis CLKI_DIV 	= "1" */
    /* synthesis CLKFB_DIV 	= "5" */
    /* synthesis CLKOP_DIV 	= "4" */
    /* synthesis CLKOK_DIV 	= "2" */
    /* synthesis DELAY_CNTL 	= "STATIC" */
    /* synthesis FDEL 		= "0" */
    /* synthesis WAKE_ON_LOCK 	= "ON" */
    /* synthesis PHASEADJ 	= "270" */
    /* synthesis DUTY 		= "4" */
    /* synthesis LOCK_CYC 	= "16" */
    ;

endmodule
