/****************************************************************
-- Copyright (c) 2003 - Lattice Semiconductor Corporation
--                    - NetCom IP
--
-- This program is controlled by a written license agreement.
-- Unauthorized Reproduction or Use is Expressly Prohibited.
-- **************************************************************/

// file name:	fcram_ui_drv.v
// version:	1.0
// date:	Nov 18, 2003 
// 
// code type:	RTL Level
//
// Overview:	This module is a "dummy" model used to interface
//		with the user side of the fcram controller. It 
//		is a place holder for the user's application and
//		is included just to go through the synthesis flow.
//
// Rev:		0.0 - Initial Ver N.G, M.P.H
/***************************************************************/

`timescale 1ns/100ps

`include "fcram_params.v"

// DEFINES


module fcram_app_drv(

		//signals tied to fcram_top "external" pins
		sys_resetn,
                usr_reset, 
                usr_clk,  
                usr_addri,  
                usr_cmdi,    
                usr_datai,   
                usr_datao,    
                usr_num_xfersi, 
                usr_acko,        
                usr_dreqo,    
                usr_dvalo,     
                init_bt, 
                init_te,
                init_de,
                init_dic,   
                ref_burst, 
                ref_interval,
                ctrl_ref_eni,       

		//signals tied to internal instances in fcram_top 
                usr_reset_int,
                usr_addri_int, 
                usr_cmdi_int,   
                usr_datai_int,  
                usr_datao_int,   
                usr_num_xfersi_int,
                usr_acko_int,    
                usr_dreqo_int,
                usr_dvalo_int,
                init_bt_int,
                init_te_int,
                init_de_int,
                init_dic_int,   
                ref_burst_int, 
                ref_interval_int,
                ctrl_ref_eni_int


		);

// -----------------------
// USER DEFINED PARAMETERS
// -----------------------

parameter dq_width = `DQ_WIDTH;         // width of FCRAM data bus (8, 16, 32 bits)
parameter dq_groups = `DQ_GROUPS;  // number of data bus groups (groups of 8)

`ifdef DQ_WIDTH8 // UD_WIDTH = 16
   parameter usr_dat_width = 16;        // width of user data bus is 16 bits
`endif

`ifdef DQ_WIDTH9 // UD_WIDTH = 18
   parameter usr_dat_width = 18;        // width of user data bus is 18 bits
`endif

`ifdef DQ_WIDTH16 // UD_WIDTH = 32
   parameter usr_dat_width = 32;        // width of user data bus is 32 bits
`endif

`ifdef DQ_WIDTH18 // UD_WIDTH = 36
   parameter usr_dat_width = 36;        // width of user data bus is 36 bits
`endif

`ifdef DQ_WIDTH36 // UD_WIDTH = 72
   parameter usr_dat_width = 72;        // width of user data bus is 72 bits
`endif


        // fcram user interface IO ports

	output  [usr_dat_width-1:0] usr_datao;	// read data from fcram cntlr usr intf.
	reg  [usr_dat_width-1:0] usr_datao_ff  /* synthesis syn_useioff = 0 */;	
	output  usr_acko;			// fcram cntlr ackonowledge
	reg  usr_acko_ff /* synthesis syn_useioff = 0 */;
	output  usr_dreqo;			// fcram cntlr write data request to user 
	reg  usr_dreqo_ff /* synthesis syn_useioff = 0 */;
	output  usr_dvalo;			// read data from cntrl is valid 
	reg  usr_dvalo_ff /* synthesis syn_useioff = 0 */;

	input usr_reset;				// reset to fcram cntlr usr intf - active high 
		
	input usr_clk;				// clock to fcram cntlr usr intf

	input [26:0] usr_addri;			// address usr_addri = {bank(2),row(15),col(10)}

	input [2:0] usr_cmdi;			// user interface commands - nop, wr , rd, self_ref,auto_ref
		
	input [usr_dat_width-1:0] usr_datai;	// write data to fcram cntlr usr intf.


	input [3:0] usr_num_xfersi;		// number of UD_WIDTH - bit data values to transfer 


	input [1:0] init_dic;			// DIC(2)
						
	input init_de;		        // DS
						
	input init_te;		        // TE
						
	input init_bt;	        	// BT
						
						

	input [3:0]ref_burst;		// refresh burst counter  
	
	input [15:0]ref_interval;		// refresh interval counter 

	input ctrl_ref_eni;			// Enable refresh by fcram cntlr

	input sys_resetn;


        // fcram user interface ports

	input  [usr_dat_width-1:0] usr_datao_int;	// read data from fcram cntlr usr intf.
	reg  [usr_dat_width-1:0] usr_datao_int_ff;	// read data from fcram cntlr usr intf.
	input  usr_acko_int;				// fcram cntlr ackonowledge
	reg  usr_acko_int_ff;				// fcram cntlr ackonowledge
	input  usr_dreqo_int;			// fcram cntlr write data request to user 
	reg  usr_dreqo_int_ff;			// fcram cntlr write data request to user 
	input  usr_dvalo_int;			// read data from cntrl is valid 
	reg  usr_dvalo_int_ff;			// read data from cntrl is valid 

	output usr_reset_int;				// reset to fcram cntlr usr intf - active high 
	wire usr_reset_int;	
		
	wire usr_clk_int;

	output [26:0] usr_addri_int;			// address usr_addri = {bank(2),row(15),col(10)}
	reg [26:0] usr_addri_int_ff /* synthesis syn_useioff = 0 */;

	output [2:0] usr_cmdi_int;			// user interface commands - nop, wr , rd, self_ref,auto_ref
							//                           00x, 100, 110,   101     111 
	reg [2:0] usr_cmdi_int_ff /* synthesis syn_useioff = 0 */;	
		
	output [usr_dat_width-1:0] usr_datai_int;	// write data to fcram cntlr usr intf.
	reg [usr_dat_width-1:0] usr_datai_int_ff /* synthesis syn_useioff = 0 */;


	output [3:0] usr_num_xfersi_int;			// number of UD_WIDTH - bit data values to transfer 
	reg [3:0] usr_num_xfersi_int_ff /* synthesis syn_useioff = 0 */;


			                        // initialization parameters = {DIC(2),DS,TE,CL(3),BT,BL(3)}
	output [1:0] init_dic_int;		// DIC(2)
	reg [1:0] init_dic_int_ff /* synthesis syn_useioff = 0 */;
						// -----------------------------
	                                        // DIC[1:0] - Output Driver Impedance control
						//     0 0    Normal output driver
						//     0 1    Strong output driver
						//     1 0    Weaker output driver
						//     1 1    Weakest output driver
						// -----------------------------
						
	output init_de_int;		        // DS
	reg init_de_int_ff /* synthesis syn_useioff = 0 */;
						// -----------------------------
						// DS - DLL Switch 
						// 0    DLL Enable
						// 1    DLL Disable
						// -----------------------------
						
	output init_te_int;		// TE
	reg init_te_int_ff /* synthesis syn_useioff = 0 */;
						// -----------------------------
						// TE - Test Mode
						// 0    Regular 
						// 1    Test Mode Entry
						// -----------------------------
						
	output init_bt_int;		// BT
	reg init_bt_int_ff /* synthesis syn_useioff = 0 */;
						// -----------------------------
						// BT - Burst Type
						// 0    Sequential
						// 1    Interleave
						// -----------------------------
						
						

	output [3:0]ref_burst_int;		// refresh burst counter  
	reg    [3:0]ref_burst_int_ff /* synthesis syn_useioff = 0 */;		 
	
	output [15:0]ref_interval_int;		// refresh interval counter 
	reg    [15:0]ref_interval_int_ff /* synthesis syn_useioff = 0 */;		

	output ctrl_ref_eni_int;			// Enable auto refresh by fcram cntlr
	reg ctrl_ref_eni_int_ff /* synthesis syn_useioff = 0 */;


	assign  usr_reset_int = usr_reset; 


	// if running a simulation, the flip-flops in the user application driver are
	// bypassed, they are only needed during synthesis to prevent user i/o from
	// routing to primary fpga pads
        assign usr_addri_int      = usr_addri_int_ff;  
        assign usr_cmdi_int       = usr_cmdi_int_ff;    
        assign usr_datai_int      = usr_datai_int_ff;   
        assign usr_num_xfersi_int = usr_num_xfersi_int_ff; 
        assign init_dic_int       = init_dic_int_ff;    
        assign init_de_int        = init_de_int_ff; 
        assign init_te_int        = init_te_int_ff; 
        assign init_bt_int        = init_bt_int_ff; 
        assign ref_burst_int      = ref_burst_int_ff;  
        assign ref_interval_int   = ref_interval_int_ff; 
        assign ctrl_ref_eni_int   = ctrl_ref_eni_int_ff; 

        assign usr_acko           = {1{init_de}} | usr_acko_int_ff;    
        assign usr_datao          = {usr_dat_width{init_de}} | usr_datao_int_ff;   
        assign usr_dreqo          = {1{init_de}} | usr_dreqo_int_ff;
        assign usr_dvalo          = {1{init_de}} | usr_dvalo_int_ff;


	always@(posedge usr_clk or negedge sys_resetn) begin
	  if (!sys_resetn) begin

                usr_addri_int_ff <= 0; 
                usr_cmdi_int_ff <= 0;   
                usr_datai_int_ff <= 0;  
                usr_num_xfersi_int_ff <= 0;
                init_dic_int_ff <= 0;   
                init_de_int_ff <= 0;
                init_te_int_ff <= 0;
                init_bt_int_ff <= 0;
                ref_burst_int_ff <= 0; 
                ref_interval_int_ff <= 0;
                ctrl_ref_eni_int_ff <= 0;

                usr_acko_ff <= 0;    
                usr_datao_ff <= 0;   
                usr_dreqo_ff <= 0;
                usr_dvalo_ff <= 0;

	  end
	  else begin

                usr_addri_int_ff <= usr_addri | {27{init_de}}; 
                usr_cmdi_int_ff <= usr_cmdi | {3{init_de}};   
                usr_datai_int_ff <= usr_datai | {usr_dat_width{init_de}};  
                usr_num_xfersi_int_ff <= usr_num_xfersi | {4{init_de}};
                init_dic_int_ff <= init_dic | {2{init_de}};   
                init_de_int_ff <= init_de | {1{init_de}};
                init_te_int_ff <= init_te | {1{init_de}};
                init_bt_int_ff <= init_bt | {1{init_de}};
                ref_burst_int_ff <= ref_burst | {4{init_de}}; 
                ref_interval_int_ff <= ref_interval | {16{init_de}};
                ctrl_ref_eni_int_ff <= ctrl_ref_eni | {1{init_de}};

                usr_acko_int_ff <= usr_acko_int;    
                usr_datao_int_ff <= usr_datao_int;   
                usr_dreqo_int_ff <= usr_dreqo_int;
                usr_dvalo_int_ff <= usr_dvalo_int;

	  end
        end // always@( posedge fpga_clk )
// -------------------------------------------------------------------------------------------------------
// -------------------------------------------------------------------------------------------------------
// *******************************************************************************************************



endmodule

