Introduction
============

This document describes the operation and use of a test bitstream for the FCRAM interface on the LatticeEC™-
Advanced evaluation board. This design implemented by Verilog language is targeted to LFEC20E-5 for running 
FCRAM memory test at 133.33MHz.

The bitstream described in this document was developed using the Lattice FCRAM I Controller for
LatticeECP/EC™(FCRAM-ONE-E2-N1). More information on this IP core can be found on the Lattice web site at: 
www.latticesemi.com/ip.

The LatticeEC Advanced Evaluation Board features an on-board FCRAM, TOSHIBA TC59LM806CFT-50. See the Users 
Manual of the board for further information.

For LatticeECP/EC™ family, two bitstream files are included in the ZIP file included with this document for 
the support of the following frequencies:

fcram_verilog_pnr_133MHz.bit


Board Setup
===========

1. Set the VCCIO pins of all banks to 2.5V by putting all eight jumpers of JP2-JP5 to JP4.
2. Push SW4 down.
3. Set all three pins (CFG2, CFG1, CFG0) of SW5 ON. (Push all SW5 pins down.)
4. SW1 pin 1 is the “rst_n” reset signal. This needs to be pulled up to lease the reset state.
5. (Rev-C PCB and later only): Located on the 3-pin header between SW4 and SW5.  Select 2.5V 
   by moving jumper to the lower two pins.
6. The 33.33MHz oscillator must be installed in pins 2, 8 (GND), 9 (CLK) and 15 (3.3V) of the 
   DIP-16 socket.  This will provide a clock signal to the FPGA through ball F6.
7. Use a 5V power supply that can provide adequate current to the board.

Memory Testing Algorithm:
=========================

The test is completed by writing test_data into address space (from 0 to 1FFFFFE) 
of the user interface and then read the data back for checking.

The test starts from writing 0x01 to byte_1 (D15-D8) and 0xfe to byte_0 (D7-D0) 
of address 0x0000000, then the test data will be rotated within the byte and the 
address will be increased by 2 for the next write cycle.

When the write reaches address 0x1fffffe, reading and verification will be started 
from address 0x0000000, and then address 0x0000002, ...

After the read reaches address 0x1fffffe, one test is considered as completed and 
the test_data will be changed for the next test.

In order to prevent writing the same pattern to the same address location for 
every test, the test_data is rotated and then inverted at address 0x0000000 before 
a new test starts.

The following are the testing sequences:

                             byte_1  byte_0
                             D15-D8  D7-D0
Test 1 started----------------------------
Write to address 0x0000000:  0x01    0xfe
Write to address 0x0000002:  0x02    0xfd
Write to address 0x0000004:  0x04    0xfb
Write to address 0x0000006:  0x08    0xf7
Write to address 0x0000008:  0x10    0xef
Write to address 0x000000A:  0x20    0xdf
Write to address 0x000000C:  0x40    0xbf
Write to address 0x000000E:  0x80    0x7f
Write to address 0x0000010:  0x01    0xfe
Write to address 0x0000012:  0x02    0xfd
Write to address 0x0000014:  0x04    0xfb
Write to address 0x0000016:  0x08    0xf7
 :
 :
Write to address 0x1fffffe:  0x80    0x7f
Read from address 0x0000000
Read from address 0x0000002
 :
 :
Read from address 0x1fffffe
Test 2 started----------------------------
Write to address 0x0000000:  0xfd    0x02
Write to address 0x0000002:  0xfb    0x04
Write to address 0x0000004:  0xf7    0x08
Write to address 0x0000006:  0xef    0x10
Write to address 0x0000008:  0xdf    0x20
Write to address 0x000000A:  0xbf    0x40
Write to address 0x000000C:  0x7f    0x80
Write to address 0x000000E:  0xfe    0x01
Write to address 0x0000010:  0xfd    0x02
Write to address 0x0000012:  0xfb    0x04
Write to address 0x0000014:  0xf7    0x08
Write to address 0x0000016:  0xef    0x10
 :
 :
Write to address 0x1fffffe:  0xfe    0x01
Read from address 0x0000000
Read from address 0x0000002
 :
 :
Read from address 0x1fffffe
Test 3 started----------------------------
Write to address 0x0000000:  0x04    0xfb
Write to address 0x0000002:  0x08    0xf7
Write to address 0x0000004:  0x10    0xef
Write to address 0x0000006:  0x20    0xdf
Write to address 0x0000008:  0x40    0xbf
Write to address 0x000000A:  0x80    0x7f
Write to address 0x000000C:  0x01    0xfe
Write to address 0x000000E:  0x02    0xfd
Write to address 0x0000010:  0x04    0xfb
Write to address 0x0000012:  0x08    0xf7
Write to address 0x0000014:  0x10    0xef
Write to address 0x0000016:  0x20    0xdf
 :
 :
Write to address 0x1fffffe:  0x02    0xfd
Read from address 0x0000000
Read from address 0x0000002
 :
 :
Read from address 0x1fffffe
Test 3 started----------------------------
Write to address 0x0000000:  0xf7    0x08
 :
 :
 
Test results:
=============

There are two counters implemented for showing the number of successful tests 
and failed tests.

While reading data back for verification, if any data in any address location 
is incorrect, the failure counter will be increased by one.

Only if all the data in all address locations are correct, the success counter 
will be increased.

   number_of_tests_passed: displayed on LEDs D8(MSB), D7, D6, D5(LSB)
   number_of_tests_failed: displayed on LEDs D4(MSB), D3, D2, D1(LSB)

Waveform Measuring:
===================

For measuring write cycle timing, set trigger at falling edge of ball AE10 (signal fsm2).

For measuring read cycle timing, set trigger at rising edge of ball AE10 (signal fsm2).
