// Copyright (c) 2003 - Lattice Semiconductor
//                    - November 2003.
//
// This program is controlled by a written license agreement.
// Unauthorized Reproduction or Use is Expressly Prohibited.
// ********************************************************************
//
//
//  Name   : fpga_io
//
//  Parent : fcram_top
//
//  Children : 
//
//  Overview: FPGA I/O buffers and flip flops.
//
//  Log:
//
//  Revision 1.0 11/05/03 Mike Hammer
//                        Nav Gupta
//
//  Initial revision
//  Modified :  
//
// *********************************************************************

`timescale 1 ns/100 ps

`include "fcram_params.v"

module fpga_io (

   sys_reset,      // system reset (active high)
   sys_clkp_90,

   pdn,
   csn,
   fn,
   ba,
   addr,

   ddr_pdn,
   ddr_csn,
   ddr_fn,
   ddr_ba,
   ddr_addr
) ;
  

// -----------------------
// USER DEFINED PARAMETERS
// -----------------------

parameter dq_width = `DQ_WIDTH;    // width of FCRAM data bus (8, 16, 32 bits)
parameter dq_groups = `DQ_GROUPS;  // number of data bus groups (groups of 8)

input          sys_reset;          // system reset (active high)
input          sys_clkp_90;

output         ddr_pdn;
output         ddr_csn;
output         ddr_fn;
output [14:0]  ddr_addr;
output [1:0]   ddr_ba;

input          pdn;
input          csn;
input          fn;
input [14:0]   addr;
input [1:0]    ba;

wire            pdn_buf;
wire            csn_buf;
wire            fn_buf;
wire [14:0]     addr_buf;
wire [1:0]      ba_buf;

// ------------
//  DDR ADDRESS
// ------------


OB OB_addr0 (.I(addr_buf[0]),.O(ddr_addr[0])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr0 (

   .D    (addr[0]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[0])
);

OB OB_addr1 (.I(addr_buf[1]),.O(ddr_addr[1])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr1 (

   .D    (addr[1]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[1])
);

OB OB_addr2 (.I(addr_buf[2]),.O(ddr_addr[2])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr2 (

   .D    (addr[2]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[2])
);

OB OB_addr3 (.I(addr_buf[3]),.O(ddr_addr[3])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr3 (

   .D    (addr[3]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[3])
);

OB OB_addr4 (.I(addr_buf[4]),.O(ddr_addr[4])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr4 (

   .D    (addr[4]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[4])
);

OB OB_addr5 (.I(addr_buf[5]),.O(ddr_addr[5])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr5 (

   .D    (addr[5]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[5])
);

OB OB_addr6 (.I(addr_buf[6]),.O(ddr_addr[6])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr6 (

   .D    (addr[6]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[6])
);

OB OB_addr7 (.I(addr_buf[7]),.O(ddr_addr[7])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr7 (

   .D    (addr[7]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[7])
);

OB OB_addr8 (.I(addr_buf[8]),.O(ddr_addr[8])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr8 (

   .D    (addr[8]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[8])
);

OB OB_addr9 (.I(addr_buf[9]),.O(ddr_addr[9])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr9 (

   .D    (addr[9]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[9])
);

OB OB_addr10 (.I(addr_buf[10]),.O(ddr_addr[10])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr10 (

   .D    (addr[10]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[10])
);

OB OB_addr11 (.I(addr_buf[11]),.O(ddr_addr[11])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr11 (

   .D    (addr[11]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[11])
);

OB OB_addr12 (.I(addr_buf[12]),.O(ddr_addr[12])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr12 (

   .D    (addr[12]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[12])
);

OB OB_addr13 (.I(addr_buf[13]),.O(ddr_addr[13])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr13 (

   .D    (addr[13]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[13])
);

OB OB_addr14 (.I(addr_buf[14]),.O(ddr_addr[14])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_addr14 (

   .D    (addr[14]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (addr_buf[14])
);


// ------------
// BANK ADDRESS
// ------------

OB OB_ba0 (.I(ba_buf[0]),.O(ddr_ba[0])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_ba0 (

   .D    (ba[0]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (ba_buf[0])
);

OB OB_ba1 (.I(ba_buf[1]),.O(ddr_ba[1])) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_ba1 (

   .D    (ba[1]),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (ba_buf[1])
);

// ---------------
// CONTROL SIGNALS
// ---------------

OB OB_pdn (.I(pdn_buf),.O(ddr_pdn)) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_pdn (

   .D    (pdn),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (pdn_buf)
);

OB OB_csn (.I(csn_buf),.O(ddr_csn)) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3BX OFS1P3BX_ddr_csn (

   .D    (csn),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .PD   (sys_reset),
   .Q    (csn_buf)
);

OB OB_fn (.I(fn_buf),.O(ddr_fn)) /* synthesis IO_TYPE="SSTL25_II" */;

OFS1P3DX OFS1P3DX_ddr_fn (

   .D    (fn),
   .SP   (1'b1),
   .SCLK (~sys_clkp_90),
   .CD   (sys_reset),
   .Q    (fn_buf)
);

endmodule
