// Copyright (c) 2003 - Lattice Semiconductor
//
// This program is controlled by a written license agreement.
// Unauthorized Reproduction or Use is Expressly Prohibited.
// ********************************************************************
//
//
//  Name   : fcram_core
//
//  Parent : fcram_top
//
//  Children : 
//
//  Overview: FCRAM controller.
//
//  Log:
//
//  Revision 1.0 11/17/03 Mike Hammer
//                        Nav Gupta
//
//  Initial revision
//  Modified :  
//
// *********************************************************************

`timescale 1 ns/100 ps

`include "fcram_params.v"

module fcram_one_e2_1_001 (

    sys_reset,              // active high system reset
    sys_clkp_90,            // system clock 
    sys_clk_0,              // system clock (-90 degree phase shift from sys_clkp_90)

    usr_reset,              // active high user reset
    usr_addri,              // user read/write address input
    usr_cmdi,               // user command input
    usr_datai,              // user write data input
    usr_datao,              // user read data output
    usr_num_xfersi,         // user supplied number of transfers
    usr_acko,               // user command acknowledge output
    usr_dreqo,              // user write data advance request outptu
    usr_dvalo,              // user read data valid output
    usr_read_delay,         // user read delay inputs
    bt,                     // burst type (0=sequential; 1=interleaved)
    te,                     // test mode (0=regular; 1=test mode entry)
    de,                     // dll enable (0=dll enable; 1=dll disable)
    dic,                    // output driver impedance control 
                            //    (00=normal output driver)
    ref_burst,              // refresh burst number (1-15)
    ref_interval,           // refresh interval count (clock cycles)
    cntrl_ref_eni,          // controller refresh initiated refresh enable

    pdn,                    // power-down signal to FCRAM
    csn,                    // active low chip select to FCRAM
    fn,                     // function select signal to FCRAM
    ba,                     // bank address to FCRAM
    addr,                   // address to FCRAM
    dout0,                  // data out to ddr interface
    dout1,                  // data out to ddr interface
    dout_val,               // active high data out valid
    din0,                   // read data from FCRAM ddr interface
    din1,                   // read data from FCRAM ddr interface
    dqs_en,                 // DQS enable to ddr interface
    dqs_low,                // DQS low signal to ddr interface

`ifdef TECH_EC
    dcntl_enbl,
    data_valid,
    ddrclkpol,
`endif

    pll_lock,               // pll lock
    dqsbuf_read             // read signal (resets the preamble detector)
) /* synthesis syn_black_box */;             

// -----------------------
// USER DEFINED PARAMETERS
// -----------------------

parameter dq_width     = `DQ_WIDTH;     // width of FCRAM data bus (8, 9, 16, 18, or 36 bits)
parameter dq_groups    = `DQ_GROUPS;    // number of data bus groups (groups of 8)
parameter row_num_bits = `NUM_ROW_BITS; // number of rows in FCRAM
parameter col_num_bits = `NUM_COL_BITS; // number of columns in FCRAM

input         sys_reset;
input         sys_clkp_90;
input         sys_clk_0;

input         usr_reset;
input [26:0]  usr_addri;
input [2:0]   usr_cmdi;
input  [(dq_width*2)-1:0] usr_datai;
output [(dq_width*2)-1:0] usr_datao;
input [3:0]   usr_num_xfersi;
output        usr_acko;
output        usr_dreqo;
output        usr_dvalo;
input [1:0]   usr_read_delay;

input         bt;
input         te;
input         de;
input [1:0]   dic;

input [15:0]  ref_interval;
input [3:0]   ref_burst;
input         cntrl_ref_eni;

output        pdn;
output        csn;
output        fn;
output [14:0] addr;
output [1:0]  ba;

output        dout_val;
output        dqs_en;
output        dqs_low;

output [dq_width-1:0]   dout0;
output [dq_width-1:0]   dout1;

input [dq_width-1:0]    din0;
input [dq_width-1:0]    din1;

input         pll_lock;

`ifdef TECH_EC
output        dcntl_enbl;
input [dq_groups-1:0] data_valid;
input [dq_groups-1:0] ddrclkpol;
`endif

output        dqsbuf_read;             // read signal to the DQSBUF module 
                                       // to reset the preamble detector

endmodule
