|
Copyright 2000-2004 © Lattice
Semiconductor Corporation. ALL RIGHTS RESERVED. This confidential and
proprietary software may be used only as authorized by a licensing agreement from
Lattice Semiconductor Corporation. The entire notice above must be reproduced
on all authorized copies and copies may only be made to the extent permitted by
a licensing agreement from Lattice Semiconductor Corporation.
|
Mail: |
Lattice
Semiconductor Corporation |
|
Telephone: |
1-800-Lattice
(USA and Canada) |
|
|
1-408-826-6000
(other locations) |
|
Website: |
|
|
E-mail: |
|
IP Name: |
10/100 Ethernet MAC |
|
|
IP Version: |
Ver3 |
|
|
IP
Configuration Release Date: |
July 30, 2004 |
|
|
Configuration
Description: |
10/100 Ethernet Mode |
|
|
Target
Technology: |
EC |
|
Synthesis Tools Supported: |
Synplify
for Lattice 7.6.a |
|
|
LeonardoSpectrum
2004a.53_OEM_Lattice |
|
Simulation
Tools Supported: |
ModelSim Modelsim
SE 5.8d |
|
Lattice
Tool Supported: |
ispLEVER |
ispLeverCORE
§ Stand-Alone Quick-Start Tutorial
§ Interactive Quick-Start Tutorial
§ Detailed Tutorial
The
Interactive Quick-Start Tutorial is an interactive HTML-based tutorial
available for this ispLeverCORE IP module. It links to the IP core's Readme
file to provide a one-stop reference to all of the core's usage documentation.
To install the Interactive Quick-Start Tutorial:
1. Download and install an ispLeverCORE IP Evaluation Package onto your computer.
2. Download the Interactive Quick-Start Tutorial (ispLeverCORE tutorial.zip) from the Lattice website:
3. Extract the contents of ispLeverCORE tutorial.zip into the /tutorial directory inside the installed ispLeverCORE IP core.
4. Run the ispLeverCORE IP Evaluation Tutorial. Click on this link and the Tutorial will be connected to the core's ReadMe.
The simulation script(s) provided in the simulation/scripts directory must be modified to properly locate the ispLEVER installation directory. Find the line shown below and modify the directory information.
set isplever_dir C:/ispTOOLS
|
All Lattice IP cores are available in the ZIP file format. Unzip the
file to the directory location of choice. Refer to the directory structure
section for detailed information of the packaged files. Files for Synthesis
A set of HDL files (Verilog and/or VHDL) are provided for synthesis.
These design files are provided such that this IP core can be evaluated as a
stand-alone device or as part of an application specific design. The files
are located in: ether_fast_e2_3_006/ec/ver1/source. §
ts_ethmac_top.v - The
top-level source file is divided into two sections. The I/O section and the
Core section. The I/O section includes all I/O components (inferred during synthesis
or instantiated technology elements). The Core section instantiates the Core
as a black box within the design. The top-level source file can be used as
the platform for an application specific design that includes/integrates this
IP core. §
ether_fast_e2_3_006_params.v - The ether_fast_e2_3_006_params.v is used to specify the
configuration of this IP core. This file must be compiled along with the
top-level source file during synthesis. NOTE: THIS FILE AND ALL IP PARAMETER FILES MUST NOT BE
MODIFIED IN ANY WAY. IF THIS FILE IS MODIFIED THIS IP core MAY NOT RUN AT
SPECIFICATION. §
ec_syn_lib.v - This
file contains the instantiation of all EC synthesis library. § feth_hclk_pll.v
- This file contains the
instantiation of PLL. This file is present only if PLL is required by the IP
core. § feth_rx_pll.v
- This file contains the
instantiation of PLL. This file is present only if PLL is required by the IP
core. §
ether_fast_e2_3_006.v
- This file
contains the synthesis directives that allow the core section to be treated
as a "black box" during synthesis in Synplicity's Synplify and
Leonardo Spectrum. This file
represents the top-level of the core Section. |
After Synplify is running, add
these files in the following order:
~/source/ether_fast_e2_3_006_params.v
~/source/ec_syn_lib.v
~/source/feth_hclk_pll.v
~/source/feth_rx_pll.v
~/source/ether_fast_e2_3_006.v
~/source/ts_ethmac_top.v
~/source
In the Implementation Options dialog box set the following options
under Device tab:
§
Lattice Technology = LATTICE-EC
§
Part = LFEC20E
§
Speed = 4
§
Package = FPBGA672
§
Set value of Fanout
Guide = 100
Under the Options tab set the following Optimization Switches:
§
FSM Compiler Enable
§
Resource Sharing Enable
§
Frequency 80 MHz
Under the Constraints tab set the following Optimization Switches:
§
Use Clock Period For
Unconstrainted IO Enable
Under the Verilog tab set the following Optimization Switches:
§
Use Verilog 2001 Disable
Select Run
Using the FlowTabs setup select the following options:
Under Technology Tab
§
Lattice Technology = LATTICE-EC
§
Device = LFEC20E
§
Speed = -4
§
Package = FPBGA672
§
Select Apply
Under Input Tab open the following files:
~/source/ether_fast_e2_3_006_params.v
~/source/feth_hclk_pll.v
~/source/feth_rx_pll.v
~/source/ether_fast_e2_3_006.v
~/source/ts_ethmac_top.v
Select the Verilog Options tab at the bottom of the page.
§
Top Module = ts_ethmac_top
§
Select Apply
§
Select Run Flow
In the Device Selector dialog box, select the following:
§
Family = Lattice
EC
§
Device = LFEC20E
§
Speed Grade =4
1) Make sure the following evaluation and preference files from /par/
are placed/located in the project directory:
§
ether_fast_e2_3_006.ld2 for XPGA or .ngo for ORCA
§
ether_fast_e2_3_006.lct for XPGA or .prf for ORCA
Note: Multiple preference files may be available in
the package. Use the preference file, labeled in accordance with the synthesis
tool used to generate the EDIF netlist.
§
ether_fast_e2_3_006_synplify.lct or .prf for Synplify
§
ether_fast_e2_3_006_leonardo.lct or .prf for LeonardoSpectrum
2) Top-level EDIF netlist generated from running synthesis.
3) Rename the .lct or .prf (in step 2) to match the project name. For
example, if the project name is "demo.syn", then the .lct or .prf
must be renamed to demo.lct or demo.prf.
§
Import the EDIF netlist into the project.
§
In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options.
The Timing Checkpoint Options window should pop-up. In both sections Before
Route and After Route, select continue for If Checkpoint Fails. Some designs
are over-constrained to obtain timing results. These over-constraints may not
be met which will cause disruption in the design run, unless we choose to
continue
§
In the ispLEVER Project Navigator, right-click on Map Design and select
Properties. Set the following Properties as required per design. The following
options are suggested values for the top-level design provided:
~ Pack
Logic Block Util.: 5
All other
options remain at their default values.
§
In the ispLEVER Project Navigator, right-click on Place & Route
Design and select Properties. Set the following Properties as required per
design. The following options are suggested values for the top-level design
provided:
~ Placement
Effort Level: 5
~ Routing
Passes: 15
~ Placement
Iterations: 1
~ Placement
Iteration Start Pt: 1
~ Placement
Save Best Run: 1
~ Routing
Resource Optimization: 5
~ Routing
Delay Reduction Pass: 5
All other
options remain at their default values.
§
Select Place & Route Trace Report in the Project Navigator to
execute Place and Route and generate a timing report.
Some cores are overconstrained to achieve maximum timing performance.
The user may observe timing violations when viewing the timing report. To
obtain actual results, use the Post Route Trace preference files to
generate the correct timing report.
1) Replace the preference file (.lct or .prf) in the project directory
with the following Post Route Trace file. Rename the Post Route Trace
preference file to match the project name.
§
post_route_trace_synplify.lct or .prf for Synplify
§
post_route_trace_leonardo.lct or .prf for LeonardoSpectrum
2) From the GUI of the Project Navigator, right click on Post_Route_Timing_Report
(for XPGA) or Place_Route_Trace_Report (for ORCA). Select Force One
Level