10/100Mbps Ethernet MAC Readme

General Information

Copyright Notice

Copyright 2000-2004 © Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This confidential and proprietary software may be used only as authorized by a licensing agreement from Lattice Semiconductor Corporation. The entire notice above must be reproduced on all authorized copies and copies may only be made to the extent permitted by a licensing agreement from Lattice Semiconductor Corporation.

Contacting Lattice

Mail:

Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR  97124
U.S.A.

Telephone:

1-800-Lattice (USA and Canada)

 

1-408-826-6000 (other locations)

Website:

http://www.latticesemi.com

E-mail:

techsupport@latticesemi.com

 

IP Module Information

About this Module

IP Name:

10/100Mbps Ethernet MAC

IP Version:

ver3

IP Configuration Release Date:

January, 2005

Configuration Description:

FETH_MODE=true MIIM_MODULE=true

Target Technology:

Lattice XP

 

Software Requirements

Synthesis Tools Supported:

Synplify 8.0B

 

LeonardoSpectrum 2004b.58_OEM_Lattice

Precision        2005a.122OEM_Lattice

Simulation Tools Supported:

ModelSim 6.0c

Lattice Tool Supported:

ispLEVER 5.0.00.47.15 or above

 

ispLeverCORE IP Evaluation Tutorials

ispLeverCORE™ Evaluation Tutorials can be accessed on the Lattice website. These tutorials show the flow for evaluating ispLeverCORE products within the ispLEVER suite of software design tools. The tutorial information is available in three forms:

§         Stand-Alone Quick-Start Tutorial

§         Interactive Quick-Start Tutorial

§         Detailed Tutorial

Interactive Quick-Start Tutorial

The Interactive Quick-Start Tutorial is an interactive HTML-based tutorial available for this ispLeverCORE IP module. It links to the IP core's Readme file to provide a one-stop reference to all of the core's usage documentation.  

To install the Interactive Quick-Start Tutorial:

1.     Download and install an ispLeverCORE IP Evaluation Package onto your computer.

2.     Download the Interactive Quick-Start Tutorial (ispLeverCORE tutorial.zip) from the Lattice website:

http://www.latticesemi.com/products/devtools/ip/eval_tutorial.cfm

3.     Extract the contents of ispLeverCORE tutorial.zip into the /tutorial directory inside the installed ispLeverCORE IP core.

4.     Run the ispLeverCORE IP Evaluation Tutorial.  Click on this link and the Tutorial will be connected to the core's ReadMe.

Installation Information

 

All Lattice IP cores are available in the ZIP file format. Unzip the file to the directory location of choice. Refer to the directory structure section for detailed information of the packaged files.

Files for Synthesis

A set of HDL files (Verilog and/or VHDL) are provided for synthesis. These design files are provided such that this IP core can be evaluated as a stand-alone device or as part of an application specific design. The files are located in: ether_fast_xm_3_006/xm/ver3/source/[verilog/vhdl].

§         ts_ethmac_top.v/vhd - The top-level source file is divided into two sections. The I/O section and the Core section. The I/O section includes all I/O components (inferred during synthesis or instantiated technology elements). The Core section instantiates the Core as a black box within the design. The top-level source file can be used as the platform for an application specific design that includes/integrates this IP core.

§         ether_fast_xm_3_006_params.v/vhd - The ether_fast_xm_3_006_params.v/vhd is used to specify the configuration of this IP core. This file must be compiled along with the top-level source file during synthesis.

NOTE: THIS FILE AND ALL IP PARAMETER FILES MUST NOT BE MODIFIED IN ANY WAY. IF THIS FILE IS MODIFIED THIS IP core MAY NOT RUN AT SPECIFICATION.

§         xp_syn_lib.v - This file contains the instantiation of all Magma synthesis library.

§         feth_hclk_pll.v/vhd & feth_rx_pll.v/vhd - This file contains the instantiation of PLL. This file is present only if PLL is required by the IP core.

§         ether_fast_xm_3_006.v - This file contains the synthesis directives that allow the core section to be treated as a "black box" during synthesis in Synplicity's Synplify and Leonardo Spectrum.  This file represents the top-level of the core Section.

Information for Running Synthesis Using Synplify

Adding Design Files

After Synplify is running, add these files in the following order:

For Verilog:

~/source/verilog/ether_fast_xm_3_006_params.v
~/source/verilog/xp_syn_lib.v
~/source/verilog/feth_hclk_pll.v
~/source/verilog/feth_rx_pll.v
~/source/verilog/ether_fast_xm_3_006.v
~/source/verilog/ts_ethmac_top.v

For VHDL:

~/source/vhdl/ether_fast_xm_3_006_params.vhd
~/source/vhdl/feth_hclk_pll.vhd
~/source/vhdl/feth_rx_pll.vhd
~/source/vhdl/ts_ethmac_top.vhd

 

Specifying Include Path Order Path

           ~/source/[verilog/vhdl]

Setting Implementation Options

In the Implementation Options dialog box set the following options under Device tab:

§         Lattice Technology = LATTICE-XP

§         Part = LFXP10C

§         Speed = -4

§         Package = FPBGA388

§         Set value of Fanout Guide = 100

Under the Options tab set the following Optimization Switches:

§         FSM Compiler Enable

§         Resource Sharing Enable

§         Frequency 80 MHz

Select Run

 

Information for Running Synthesis Using LeonardoSpectrum

Using the FlowTabs setup select the following options:

Setting Options

Under Technology Tab

§         Lattice Technology = LATTICE_XP

§         Device = LFXP10C-4F388CES

§         Speed = 4

§         Package = FPBGA388

§         Select Apply

Adding Design Files

Under Input Tab open the following files:

For Verilog:

~/source/ether_fast_xm_3_006_params.v
~/source/xp_syn_lib.v
~/source/feth_hclk_pll.v
~/source/feth_rx_pll.v
~/source/ether_fast_xm_3_006.v
~/source/ts_ethmac_top.v

For VHDL:

~/source/vhdl/ether_fast_xm_3_006_params.vhd
~/source/vhdl/feth_hclk_pll.vhd
~/source/vhdl/feth_rx_pll.vhd
~/source/vhdl/ts_ethmac_top.vhd

Select the Verilog Options tab at the bottom of the page.

§         Top Module = ts_ethmac_top

§         Select Apply

§         Select Run Flow

 

Information for Running Synthesis Using Precision

Adding Input Files

After Precision is running, add input files in the following order:

For Verilog:

~/source/verilog/ether_fast_xm_3_006_params.v
~/source/verilog/xp_syn_lib.v
~/source/verilog/feth_hclk_pll.v
~/source/verilog/feth_rx_pll.v
~/source/verilog/ether_fast_xm_3_006.v
~/source/verilog/ts_ethmac_top.v

For VHDL:

~/source/vhdl/ether_fast_xm_3_006_params.vhd
~/source/vhdl/feth_hclk_pll.vhd
~/source/vhdl/feth_rx_pll.vhd
~/source/vhdl/ts_ethmac_top.vhd

 

Setup Design

In the Project Settings dialog box set the following options:

§         Lattice Technology = LATTICEXP

§         Device = LFXP10C

§         Speed Grade= -4

§         Package = FPGBGA388

§         Set Frequency = 80

Select Synthesize

Implementing the IP Module Using ispLEVER

Setting the Target Device

In the Device Selector dialog box, select the following:

§         Family = Lattice XP

§         Device = LFXP10C

§         Speed Grade =-4

§         Operating Conditions =Commercial

§         Package Type =FPBGA388

Using the Evaluation Files

1) Make sure the following evaluation and preference files from the /par directory are placed and located in the project directory:

§         ether_fast_xm_3_006.ld2 for XPGA or .ngo for EC/ECP/ORCA/FPSC/XP

§         ether_fast_xm_3_006.lct for XPGA or .prf for EC/ECP/ORCA/FPSC/XP

Note: Multiple preference files may be available in the package. Use the preference file, labeled in accordance with the synthesis tool used to generate the EDIF netlist.

§         ether_fast_xm_3_006_synplify.lct or .prf for Synplify

§         ether_fast_xm_3_006_leonardo.lct or .prf for LeonardoSpectrum / Precision

2) Top-level EDIF netlist generated from running synthesis.

3) Rename the .lct or .prf (in step 2) to match the project name. For example, if the project name is "demo.syn", then the .lct or .prf must be renamed to demo.lct or demo.prf.

Implementing the design for EC/ECP/ORCA/FPSC/XP devices

§         Import the EDIF netlist into the project.

§         In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options window should pop-up. In both sections Before Route and After Route, select continue for If Checkpoint Fails. Some designs are over-constrained to obtain timing results. These over-constraints may not be met which will cause disruption in the design run, unless we choose to continue

§         In the ispLEVER Project Navigator, right-click on Map Design and select Properties. Set the following Properties as required per design. The following options are suggested values for the top-level design provided:

          ~ Pack Logic Block Util. [blank or 0 to 100]: 5

          All other options remain at their default values.

§         In the ispLEVER Project Navigator, right-click on Place & Route Design and select Properties. Set the following Properties as required per design. The following options are suggested values for the top-level design provided:

          ~ Placement Effort Level: 5

          ~ Routing Passes: 6

          ~ Placement Iterations: 1

          ~ Placement Iteration Start Pt: 1

          ~ Placement Save Best Run: 1

          ~ Routing Resource Optimization: 5

          ~ Routing Delay Reduction Pass: 5

          All other options remain at their default values.

§         Select Place & Route Trace Report in the Project Navigator to execute Place and Route and generate a timing report.

Timing Report file

Some cores are overconstrained to achieve maximum timing performance. The user may observe timing violations when viewing the timing report. To obtain actual results, use the Post Route Trace preference files to generate the correct timing report.

1) Replace the preference file (.lct or .prf) in the project directory with the following Post Route Trace file. Rename the Post Route Trace preference file to match the project name.

§         post_route_trace_synplify.lct or .prf for Synplify

§         post_route_trace_leonardo.lct or .prf for LeonardoSpectrum

2) From the GUI of the Project Navigator, right click on Post_Route_Timing_Report (for XPGA) or Place_Route_Trace_Report (for EC/ECP/ORCA/FPSC/XP). Select Force One Level

§         The new timing report is generated.