Gigabit Ethernet MAC Readme |
Copyright 2000-2004 © Lattice Semiconductor Corporation. ALL RIGHTS RESERVED. This confidential and proprietary software may be used only as authorized by a licensing agreement from Lattice Semiconductor Corporation. The entire notice above must be reproduced on all authorized copies and copies may only be made to the extent permitted by a licensing agreement from Lattice Semiconductor Corporation.
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Mail: |
Lattice Semiconductor
Corporation |
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Telephone: |
1-800-Lattice (USA and
Canada) |
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1-408-826-6000 (other
locations) |
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Website: |
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E-mail: |
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IP Name: |
Gigabit Ethernet MAC |
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IP Version: |
ver3 |
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IP Configuration Release Date: |
August, 2004 |
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Configuration Description: |
MODE = 1000Mbps CpuDataWidth = 16 MIIM = No |
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Target Technology: |
EC Series |
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Synthesis Tools Supported: |
Synplify for Lattice 7.6.a |
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LeonardoSpectrum 2004a.53_OEM_Lattice |
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Simulation Tools Supported: |
ModelSim 5.8d |
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Lattice Tool Supported: |
ispLEVER 4.1 or above |
ispLeverCORE
§ Stand-Alone Quick-Start Tutorial
§ Interactive Quick-Start Tutorial
§ Detailed Tutorial
The Interactive Quick-Start Tutorial is an interactive HTML-based tutorial available for this ispLeverCORE IP module. It links to the IP core's Readme file to provide a one-stop reference to all of the core's usage documentation.
To install the Interactive Quick-Start Tutorial:
Download and install an ispLeverCORE IP Evaluation Package onto your computer.
Download the Interactive Quick-Start Tutorial (ispLeverCORE tutorial.zip) from the Lattice website:
http://www.latticesemi.com/products/devtools/ip/eval_tutorial.cfm
Extract the contents of ispLeverCORE tutorial.zip into the /tutorial directory inside the installed ispLeverCORE IP core.
Run the ispLeverCORE IP Evaluation Tutorial. Click on this link and the Tutorial will be connected to the core's ReadMe.
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All Lattice IP cores are available in the ZIP file format. Unzip the file to the directory location of choice. Refer to the directory structure section for detailed information of the packaged files. Files for SynthesisA set of HDL files (Verilog and/or VHDL) are provided for synthesis. These design files are provided such that this IP core can be evaluated as a stand-alone device or as part of an application specific design. The files are located in: ether_1gig_e2_3_001/ec/ver3/source. § ts_ethmac_top.v - The top-level source file is divided into two sections. The I/O section and the Core section. The I/O section includes all I/O components (inferred during synthesis or instantiated technology elements). The Core section instantiates the Core as a black box within the design. The top-level source file can be used as the platform for an application specific design that includes/integrates this IP core. § ether_1gig_e2_3_001_params.v - The ether_1gig_e2_3_001_params.v is used to specify the configuration of this IP core. This file must be compiled along with the top-level source file during synthesis. NOTE: THIS FILE AND ALL IP PARAMETER FILES MUST NOT BE MODIFIED IN ANY WAY. IF THIS FILE IS MODIFIED THIS IP core MAY NOT RUN AT SPECIFICATION. § geth_div_pll.v - This file is the wapper for div PLL. This file is present only if PLL is required by the IP core. § geth_mult_pll.v - This file is the wapper for mult PLL. This file is present only if PLL is required by the IP core. § ec_syn_lib.v - This file contains the primitives of library. § ether_1gig_e2_3_001.v - This file contains the synthesis directives that allow the core section to be treated as a "black box" during synthesis in Synplicity's Synplify and Leonardo Spectrum. This file represents the top-level of the core Section. |
After Synplify is running, add these files in the following order:
~/source/ether_1gig_e2_3_001_params.v
~/source/geth_div_pll.v
~/source/geth_mult_pll.v
~/source/ec_syn_lib.v
~/source/ether_1gig_e2_3_001.v
~/source/ts_ethmac_top.v
~/source
In the Implementation Options dialog box set the following options under Device tab:
§ Lattice Technology = LATTICE-EC
§ Part = LFEC20E
§ Speed = -4
§ Package = F672C
§ Set value of Fanout Guide = 100
Under the Options tab set the following Optimization Switches:
§ FSM Compiler Enable
§ Resource Sharing Enable
§ Frequency 125 MHz
Select Run
Using the FlowTabs setup select the following options:
Under Technology Tab
§ Lattice Technology = lattice_ec
§ Device = LFEC20E
§ Speed = 4
§ Package = FPBGA
§ Select Apply
Under Input Tab open the following files:
~/source/ether_1gig_e2_3_001_params.v
~/source/geth_div_pll.v
~/source/geth_mult_pll.v
~/source/ether_1gig_e2_3_001.v
~/source/ts_ethmac_top.v
Select the Verilog Options tab at the bottom of the page.
§ Top Module = ts_ethmac_top
§ Select Apply
§ Select Run Flow
In the Device Selector dialog box, select the following:
§ Family = Lattice EC
§ Device = LFEC20E
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Speed Grade =-4
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Operating Conditions =Commercial
§ Package Type =FPBGA672
1) Make sure the following evaluation and preference files from /par are placed/located in the project directory:
§ ether_1gig_e2_3_001.ld2 for XPGA or .ngo for EC/ECP/ORCA/FPSC
§ ether_1gig_e2_3_001.lct for XPGA or .prf for EC/ECP/ORCA/FPSC
Note: Multiple preference files may be available in the package. Use the preference file, labeled in accordance with the synthesis tool used to generate the EDIF netlist.
§ ether_1gig_e2_3_001_synplify.lct or .prf for Synplify
§ ether_1gig_e2_3_001_leonardo.lct or .prf for LeonardoSpectrum
2) Top-level EDIF netlist generated from running synthesis.
3) Rename the .lct or .prf (in step 2) to match the project name. For example, if the project name is "demo.syn", then the .lct or .prf must be renamed to demo.lct or demo.prf.
§ Import the EDIF netlist into the project.
§ In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options window should pop-up. In both sections Before Route and After Route, select continue for If Checkpoint Fails. Some designs are over-constrained to obtain timing results. These over-constraints may not be met which will cause disruption in the design run, unless we choose to continue
§In the ispLEVER Project Navigator, right-click on Map Design and select Properties. Set the following Properties as required per design. The following options are suggested values for the top-level design provided:
~ Softwire LookUp Util.: 8
~ Pack Logic Block Util.: 0
§ In the ispLEVER Project Navigator, right-click on Place & Route Design and select Properties. Set the following Properties as required per design. The following options are suggested values for the top-level design provided:
~ Placement Effort Level: 5
~ Routing Passes: 15
~ Placement Iterations: 1
~ Placement Iteration Start Pt: 1
~ Placement Save Best Run: 1
~ Routing Resource Optimization: 5
~ Routing Delay Reduction Pass: 5
All other options remain at their default values.
§ Select Place & Route Trace Report in the Project Navigator to execute Place and Route and generate a timing report.
Some cores are overconstrained to achieve maximum timing performance. The user may observe timing violations when viewing the timing report. To obtain actual results, use the Post Route Trace preference files to generate the correct timing report.
1) Replace the preference file (.lct or .prf) in the project directory with the following Post Route Trace file. Rename the Post Route Trace preference file to match the project name.
§ post_route_trace_synplify.lct or .prf for Synplify
§ post_route_trace_leonardo.lct or .prf for LeonardoSpectrum
2) From the GUI of the Project Navigator, right click on Post_Route_Timing_Report (for XPGA) or
Place_Route_Trace_Report (for EC/ECP/ORCA/FPSC). Select Force One Level
§ The new timing report is generated.