1. Files in eval directory:

   /testbench/verilog/EHXPLLB.v
   /testbench/verilog/test_ts_ethmac_sim.v
   /tests/stim_tx_mac_5.v
   /simulation/verilog/scripts/eval_ts_ethmac_runsim.do 

   /testbench/vhdl/test_ts_ethmac_sim.vhd
   /simulation/vhdl/scripts/eval_ts_ethmac_runsim_vhd.do 

2. Test environment:
   1) DUT: ts_ethmac_top (instance name: U1_top_ts_ethmac)
      configuration:
      - GETH_MODE:            true
      

3. Sequence of opeartion:
       
       Generally, on transmission direction, see the data is
       passed from tx_fifodata to txd correctly with regarding
       to tx_en; On the receiving direction, data is passed
       from rxd to rx_dbout, and send to Rx FIFO using rx_write.

       This test exercises the pause functionality of the 
       MAC.  Pause frames are received by the Rx MAC at the 
       GMII interface, which are then passed on to the 
       external FIFO.  The valid pause frames cause the
       Transmit MAC to stop transmission for the duration
       specified by the pause frame.



Evaluting the core using Verilog test vectors
=====================================

   To run the simulation:

   - Invoke the Modelsim simulator and change directory
     to /simulation/verilog

   - Execute the Macro scripts/eval_ts_ethmac_runsim.do file


Evaluting the core using VHDL test vectors
=====================================

   To run the simulation:

   - Invoke the Modelsim simulator and change directory
     to /simulation/vhdl

   - Execute the Macro scripts/eval_ts_ethmac_runsim_vhd.do file

In the script Modify the path for the installation of you ispLEVER.



