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Lattice's new ispLeverCORE^TM are large, modular design blocks that can be reused and easily placed within a customer's programmable logic design. ispLeverCORE implement popular industry-standard functions, commonly known as Intellectual Property (IP) cores.

This document contains information to help you evaluate the package you have chosen. The following topics are covered:

General IP Core Information
Evaluation Process
Evaluation Appendix

I. IP Core Information

About the Core

IP Name:	Tri-speed Ethernet MAC
IP Version:	Ver3
IP Configuration Release Date:	November, 2003
Configuration Description:	Gigabit Mode, CpuDataWidth 16, MIIM No
Target Technology:	XPGA

Software Requirements

Synthesis Tools Supported:	Synplify 7.1 and UP
	Leonardo Spectrum 2003b.35 and UP
Simulation Tool Supported:	ModelSim SE PLUS 5.6a and UP
Lattice Tool Supported:	ispLEVER 3.1 and UP

Installation Procedures

All Lattice IP Cores are available in the zip file format. Unzip the file to the directory location of choice. Refer to the directory structure section for detailed information of the packaged files.

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II. IP Core Evaluation Procedures

Running Functional RTL Simulation

A simulation script file is provided in the "eval" directory for RTL simulation. The script file ether_1gig_xp_1_001_fsim.do uses pre-compiled models provided with this package. The pre-compiled library of models are located in the directory ether_1gig_xp_1_001/xpga/ver3/lib/modelsim/work

NOTE: The procedure described here is applicable ONLY when using ModelSim for simulation.

Simulation Procedures:

Launch ModelSim
Using the main GUI, change the directory location

Select: File -> Change Directory to ether_1gig_xp_1_001/xpga/ver3/eval/simulation

Execute ether_1gig_xp_1_001_fsim.do

Select: Tools -> Execute Macro -> scripts/ether_1gig_xp_1_001_fsim.do

Running Synthesis using Synplicity's Synplify

The step-by-step procedure provided below describes how to run synthesis using Synplify outside the ispLEVER project navigator.

Create a new working directory for synthesis
Launch the Synplify synthesis tool
Start a new project and add the specified files in the following order

~/source/ether_1gig_xp_1_001_params.v

~/source/ether_1gig_xp_1_001.v

~/source/lava1.v

~/source/geth_mult_pll.v

~/source/geth_div_pll.v

~/source/ether_1gig_top_xp_1_001.v

In the Implementation Options select a target device ispXPGA
Specify an EDIF netlist filename and EDIF netlist output location in the Implementation Options. This top-level EDIF netlist will be used during Place and Route.
Select Run

Running Synthesis using LeonardoSpectrum

The step-by-step procedure provided below describes how to run synthesis using Leondardo Spectrum outside the ispLEVER project navigator.

Create a new working directory for synthesis
Launch the Leonardo Spectrum synthesis tool
Start a new project and select Lattice device technology ispXPGA.
Set the source directory as the working directory
Open the specified files in the following order

~/source/ ether_1gig_xp_1_001_params.v

~/source/ether_1gig_top_xp_1_001.v

~/source/ ether_1gig_xp_1_001.v

~/source/geth_mult_pll.v

~/source/geth_div_pll.v

~/source/ lava1.v

Set the synthesis directory, created in step 1, as the path where you would like to save the output netlist.
Specify an EDIF netlist filename for the output file. This top-level EDIF netlist will be used during Place and Route.

Select Run Flow

Route (PAR) for XPGA devices in ispLEVER

The step-by-step procedure provided below describes how to run Place and Route in ispLEVER for an XPGA device.

Create a new working directory for Place and Route
Start a new project, assign a project name and select the project type as EDIF
Select an XPGA target device, with -4 speed grade and F516C package
Copy the following files to the Place and Route working directory.

a) ..\par\ether_1gig_xp_1_001.ld2

b) ..\par\ether_1gig_xp_1_001_synplify.lct (For Synplify flow)

c) ..\par\ether_1gig_xp_1_001_synplify_trace.lct (For Synplify flow)

d) ..\par\ether_1gig_xp_1_001_leonardo.lct (For Exemplar flow)

e) ..\par\ether_1gig_xp_1_001_leonardo_trace.lct (For Exemplar flow)

f) ..\par\rx_lava_ram.ldb

g) The top-level EDIF netlist generated from Running Synthesis

Source -> Import Constraint File and use the file dialog to import ether_1gig_xp_1_001_synplify.lct or ether_1gig_xp_1_001_leonardo.lct. This imports the constraints located in the *.lct file, overwriting the <project_name>.lct contents.

a) When prompted to reset the project update status, select Yes.

Import EDIF netlist into the project.

Select the Route Design in the Project Navigator to execute Place and Route for XPGA.

a) When prompted to overwrite the source constraints, select No.

Select Source -> Import Constraint File and use the file dialog to import ether_1gig_xp_1_001_synplify_trace.lct or ether_1gig_xp_1_001_leonardo_trace.lct. This imports the constraints located in the *.lct file, overwriting the <project_name>.lct contents.

a) When prompted to reset the project update status, select No.

Select the Post-Route Timing Report in the Project Navigator to generate a timing report for XPGA.

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III. IP Core Evaluation Appendix

Directory Structure

The directory structure for the Lattice ispLEVERCORE is shown below and includes the basic description of the contents.

\ether_1gig_xp_1_001

|--\Readme.htm

|--\xpga

|--\ver3

|--\source (Contents: (1) Verilog top-level source files

| for instantiation and synthesis (2) Parameter File(s)

| which contain IP specific configuration values)

|--\eval (Customer RTL functional simulation directory for

| evaluation)

| |

| |--\testbench (Contents: (1) Testbench for evaluation

| |

| |--\tests (Contents: (1) Stimulus file(s))

| |

| |--\simulation (Run/execute functional RTL simulation here.

| | Example: do script/runsim_rtl.do.)

| |

| |--\scripts (Contents: ModelSim macro (*.do) to run

| | simulation)

|--\gui_script

| | (Contents: Scripts for IP configuration using IP

| | Manager GUI. This file is present only if

| | the IP Manager of the most recent release of the

| | ispLEVER software does not contain the released

| | IP Core yet.)

|--\par (Contents:

| (1) For XPGA - .ld2 and .lct

| (2) .lpc file specifying IP Core configuration)

|--\lib

| |--\modelsim

|--\work (Contents: Compiled simulation models for Modelsim)

Files for Synthesis

A set of HDL files (Verilog ) is provided for synthesis. These design files are provided such that this IP Core can be evaluated as a stand-alone device or as part of an application specific design. The files are located in: ether_1gig_xp_1_001/xpga/ver3/source.

ether_1gig_top_xp_1_001.v

The top-level source file is divided into two sections. The I/O section and the Core section. The I/O section includes all I/O components (inferred during synthesis or instantiated technology elements). The Core section is instantiated as a black box.

The top-level source file can be used as the platform for an application -specific design that includes/integrates this IP Core. Additional modules can simply be instantiated in the source file to implement the application -specific design.

The ether_1gig_xp_1_001_params.v contains parameters used to specify the configuration of this IP Core. This file must be compiled along with the top-level source file during synthesis.

NOTE: THIS FILE AND ALL IP PARAMETER FILES MUST NOT BE MODIFIED IN ANY WAY. IF THIS FILE IS MODIFIED THIS IP CORE MAY NOT RUN AT SPECIFICATION.

ether_1gig_xp_1_001.v file

This file contains the synthesis directives that allow the Core section to be treated as a "black box" during synthesis in Synplicity's Synplify. This file represents the top-level of the Core Section.

geth_mult_pll.v and geth_div_pll.v

These files are required for PLLs.

lava1.v

This file is required for the instantiation of XPGA library primitives.

Files for Place and Route

The gate-level netlist(ether_1gig_xp_1_001.ld2) and preference/constraint file (*.lct) are located in the directory: ether_1gig_xp_1_001/xpga/ver3/par

For ispLEVERCORE devices implemented in XPGA technology:

Netlist file extension is “ld2”
Constraint file extension is “lct”

The constraint file (.lct) contains information for the ispLEVER Place and Route (PAR) tool and allows for optimum implementation of this IP Core in the target technology.

GUI support in IP Manager for Newly released Core

If the module_gen.zip file is present under the guiscript directory in this release package, it is because the ispLEVER software does not yet contain the utility that allows for the configuration of this IP Core using the IP Manager. The module_gen.zip file contains the files that allows for the configuration of this IP Core via the IP manager. The entire contents of this zip file need to be unzipped under the ispcpld directory of the ispLEVER software installed in your system.

Open the module_gen.zip file using the unzip utility.
Select the “Extract” or an equivalent command.
Unzip the file to the [ispLEVER_installed_root_directory]\ispCPLD directory.
If ispLEVER is open, exit and relaunch the tool. The IP Core will be included in the list when the Module/IPManager icon is opened.

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