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Copyright 2000-2004 © Lattice Semiconductor Corporation. ALL RIGHTS RESERVED

This confidential and proprietary software may be used only as authorized by a licensing agreement from Lattice Semiconductor Corporation. The entire notice above must be reproduced on all authorized copies and copies may only be made to the extent permitted by a licensing agreement from Lattice Semiconductor Corporation.

 

Lattice Semiconductor Corporation

Telephone:

1-800-Lattice (USA and Canada)

5555 NE Moore Court

 

1-408-826-6000 (other locations)

Hillsboro, OR 97124

Website:

http://www.latticesemi.com

U.S.A                                  

Email:

techsupport@latticesemi.com

 

Lattice's new ispLeverCORETM are large, modular design blocks that can be reused and easily placed within a customer's programmable logic design. ispLeverCORE implement popular industry-standard functions, commonly known as Intellectual Property (IP) cores.

 

This document contains information to help you evaluate the package you have chosen. The following topics are covered:

 

 

 

I. IP Core Information

About the Core

IP Name:

< xgbe_xgxs_o4_2_002>

IP Version:

<ver1.0>

IP Configuration Release Date:

<September 16, 2004>

Configuration Description:

 

Target Technology:

<ORCA4>

 

Software Requirements

Synthesis Tools Supported:

Synplify  version 7.7.0, Build 021R and up

 

Leonardo Spectrum 2004a.83_OEM_Lattice and UP

Simulation Tool Supported:

ModelSim SE PLUS 5.5f and UP

Lattice Tool Supported:

IspLEVER-Advanced 4.2  (R4.2.00.33.40.04)

 

Installation Procedures

All Lattice IP Cores are available in the zip file format. Unzip the file to the directory location of choice. Refer to the directory structure section for detailed information of the packaged files.

 

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II. IP Core Evaluation Procedures

Running Functional RTL Simulation

A simulation script file is provided in the "eval\simulation" directory for RTL simulation. The script file run_eval.bat uses precompiled models provided with this package. The XGXS design and testbench models have been compiled into the work directory in directory “eval\simulation”.  The ORCA ORT82G5 and SYSBUS models have been provided in the directory “eval\lib\modelsim” as tar.gz archives (ort82g5_work.tar.gz and sysbus_work.tar.gz). These files should be unarchived into the directory “eval\lib\modelsim” creating two compiled work directories  “eval\lib\modelsim\ort82g5_work and “eval\lib\modelsim\sysbus_work”.

 

NOTE: The procedure described here is applicable ONLY when using ModelSim for simulation.

 

Simulation Procedures:

1. Go to directory “eval\simulation”.

 

2. Type run_eval.bat

 

For more information on how to use ModelSim, please refer to the ModelSim User’s Manual.

 

 

Running Synthesis using Synplicity's Synplify

 

To synthesize the XGXS solution using Synplicity’s Synplify in one step, go to the directory “eval\synthesis\orca4\synplicity\config1” and enter “runsyn.bat”. A top-level EDIF for the application will be produced. Users may use runsyn.bat as a guide and template if they are creating their own unique system-level project.

 

The following step-by-step procedure may also be executed. Note that results may vary from those obtained with the scripted run due to small differences in options:

 

  1. Create a new working directory for synthesis.

 

  1. Launch the Synplify synthesis tool.

 

  1. Start a new project and add the specified files in the following order:

 

eval\source\synplicity\orca4_synplify.v

eval\source\xgxs_define.v

eval\source\ring_osc.v

eval\source\synplicity\xgxs_clk_mx2.v

eval\source\synplicity\xgxs_clk_tx.v

eval\source\synplicity\xgxs_sys_bus.v

eval\source\synplicity\ORT82G5_INTF.v

eval\source\synplicity\xgmii_io_if.v

eval\source\xgbe_xgxs_o4_2_002.v

           eval\source\synplicity\xgxs_top_xgmii.v

           eval\synthesis\orca4\synplicity\config1\xgxs_top.sdc

 

  1. In the Implementation Options select target device Lattice ORCA  Series 4.

 

  1. Specify an EDIF netlist filename and EDIF netlist output location in the Implementation Options. This top-level EDIF netlist will be used during Place and Route.

 

  1. In the Implementation Options, set the following:

 

-         Fanout guide : 1000

-         Enable FSM Compiler

-         Set the global frequency constraint to 160 MHz.

 

  1. Select run.

 

 

 

Running Synthesis using LeonardoSpectrum

 

To synthesize the XGXS solution using LeonardoSpectrum in one step, go to the directory “eval\synthesis\orca4\exemplar\config1” and enter “runsyn.bat”. A top-level EDIF for the application will be produced. Users may use runsyn.bat as a guide and template if they are creating their own unique system-level project.

 

 

The following step-by-step procedure may also be executed. Note that results may vary from those obtained with the scripted run due to small differences in options.

The step-by-step procedure provided below describes how to run synthesis using Leonardo Spectrum.

 

 

  1. Create a new working directory for synthesis.

 

  1. Launch the Leonardo Spectrum synthesis tool.

 

  1. Start a new project and select Lattice device technology ORCA-4E.

 

  1. Select Input tab, set the Working Directory path pointed to the source directory.

 

  1. Open the specified files in the following order:

 

eval\source\exemplar\orca4_leonardo.v

eval\source\xgxs_define.v

eval\source\ring_osc.v

eval\source\exemplar\xgxs_clk_mx2.v

eval\source\exemplar\xgxs_clk_tx.v

eval\source\exemplar\xgxs_sys_bus.v

eval\source\exemplar\ORT82G5_INTF.v

eval\source\exemplar\xgmii_io_if.v

eval\source\xgbe_xgxs_o4_2_002.v

            eval\source\exemplar\xgxs_top_xgmii.v

 

  1. In the Constraints tab, set Clock Frequency as 156 MHz.

 

  1. Select xgxs_top_xgmii.v ,  click the right mouse button, and select  from the list “Make xgxs_top_xgmii.v  Top of the Design”

 

  1. Set the synthesis directory, created in step 1, as the path where you would like to save the output netlist.

 

  1. Specify an EDIF netlist filename for the output file. This top-level EDIF netlist will be used during Place and Route.

 

  1. Click on the advanced tab icon.

 

a.      In the Technology Tab, Check the Manual GSR box, and fill “reset_n” in the Signal entry box.

b.      In the Input Tab, specify “eval/source” directory in   the Input File Search File text box.

 

  1. Select Run Flow

 

 

Running Place and Route (PAR) for ORCA devices in ispLEVER

 

Once the EDIF netlist is generated, the next step is to map, place and route the design. To map, place and route the entire XGXS solution in one step, Goto to the directory “par\orca4\config1” and type runpar.bat. This script will process the EDIF file to map, place and route the  XGXS IP solution.

 

 

 

The step-by-step procedure provided below may also be followed. Note that results may vary from those obtained with the scripted run due to small differences in options.

 

Once the EDIF netlist is generated, import the EDIF into the Project Navigator. The ispLEVER software

automatically detects the provided EDIF netlist of the instantiated IP core in the design. The step-by-step procedure provided below describes how to perform Place and Route in ispLEVER for an ORCA device:

 

  1. Create a new working directory for Place and Route.

 

  1. Start a new project, assign a project name and select the project type as EDIF.

 

  1. Select the ORT82G5 target device, with –3 speed grade and BM680 package.

 

  1. Copy the following files to the Place and Route working directory:

 

a) eval\par\xgbe_xgxs_o4_2_002.ngo

b) eval\par\xgxs_top_exemplar.prf if the EDIF was generated using Leonardo Spectrum or

eval\par\xgxs_top_synplicity.prf if the EDIF was generated using Synplicity Synplify

c) eval\source\ring_osc.nmc

d) The top-level EDIF netlist generated from running synthesis

 

  1. Rename the xgxs_top.prf file (in step 4) to match the project name. For example, if the project name is  "demo", then the .prf file must be renamed to demo.prf. The preference file name must match that of the project name.

 

  1. Import the EDIF netlist into the project.

 

  1. In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options window will pop-up. In both Checkpoint Options, select Continue.

 

  1. In the ispLEVER Project Navigator, highlight Place & Route Design, with a right mouse click select Properties. Set the following Properties:

-          Placement Iterations: 1

-          Placement Save Best Run: 1

-          Placement Iteration Start Point: “7” if the EDIF was generated using Synplify ; “2” if the EDIF was generated using Leonardo Spectrum

-          Routing Resource Optimization: 1

-          Routing Delay Reduction Passes: 6

-          Routing Passes: 25

-          Placement Effort Level: 5

All other options remain at their default values.

 

  1. Select the Place & Route Trace Report in the project navigator to execute Place and Route and generate a timing report for ORCA.

 

  1. Highlight Place & Route TRACE Report, with a right mouse click and select Force One Level. A new timing report is generated.

 

 

Note that timing results may change under different versions of synthesis tools or different releases of ispLever. In this case, multiple placement iteration may need to be run to find the one with 0 timing errors. Multiple placement iterations are run by increasing the “Placement Iterations” value.

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III. IP Core Evaluation Appendix

Directory Structure 

The directory structure for the Lattice ispLEVERCORE is shown below and includes the basic description of the contents.

 

\ xgbe_xgxs_o4_2_002                    

   |

   |--\Readme.html

   |

   |--\ver1.0

   |    |

   |    |-----\docs (Contents: User’s guide and data sheet)

   |    |

   |    |-----\eval (Customer directory for evaluation)

                 |                

                 |--\lib

                 |    |

                 |    |--\modelsim (Simulation zipped MTI compiled models )

                 |        |

                 |        |--\NOTE (INFO file)

                 |        |

                 |        |--\ort82g5_work (compiled  ORT82G5 embedded  block model)

                 |        |

                 |        |--\sysbus_work(compiled  SYSBIS embedded  block model)

                 |   

                 |--\par  (Place and route directory )

                 |    |

                 |    |--\xgbe_xgxs_o4_2_002.ngo (core ngo file)

                 |    |

                 |    |--\preference files for PAR

                 |    |

                 |    |--\orca4

                 |        |

                 |        |--\Config1 (Physical PAR directories containing executable scripts )

                 |              |

                 |              |--\README (INFO file)

                 |

                 |--\simulation (Run/execute functional RTL simulation here)

                 |    |      

                 |    |--\README (INFO file)

                 |    |                                    

                 |    |--\scripts (Contents: ModelSim macro (*.do) to run UNIX simulation)

                 |    |            

                 |    |--\pc_scripts (Contents: ModelSim macro (*.do) to run PC simulation)

                 |    |           

                 |    |  

                 |    |--\work (Contents: Will contain compiled testbench files

                 |    |             AFTER running functional RTL simulation)

                 |

                 |--\source (.contains files for synthesis and P&R)

                 |    |      

                 |    |--\exemplar (contains synthesis files for Leonardo Spectrum)

                 |    |           

                 |    |--\synplicity (contains synthesis files for Synplify)

                 |   

                 |--\synthesis  (synthesis directory )

                 |    |

                 |    |--\orca4

                 |        |

                 |        |--\exemplar (Leonardo Spectrum synthesis directory)

                 |        |    |

                 |        |    |--\Config1 (synthesis directory containing executable scripts)

                 |        |

                 |        |--\synplicity (Synplify synthesis directory)

                 |             |

                 |             |--\Config1 (synthesis directory containing executable scripts)

                 |       

                 |

                 |--\testbench (Contains: 1 Testbench for evaluation)

                 |   

                 |--\tests (Contains different possible test cases for evaluation)

 

 

 

 

Files for Synthesis

A set of HDL files (Verilog) are provided for synthesis. These design files are provided such that this IP Core can be evaluated as a stand-alone device or as part of an application specific design.

NOTE: $synthtool refers to either “synplicity” or “exemplar”

 

  1. xgxs_define.v defined parameters for the XGXS core

location: eval/source

NOTE: THIS FILE AND ALL IP PARAMETER FILES MUST NOT BE MODIFIED IN ANY WAY. IF THIS FILE IS MODIFIED THIS IP CORE MAY NOT RUN AT SPECIFICATION.

 

  1. xgbe_xgxs_o4_2_002.v black box for the XGXS core

location: eval/source

 

  1. xgmii_io_if.v for the DDR interface;

location: eval/source/$synthtool

 

  1. ORT82G5_INTF.v for the ORT82G5 module;

location: eval/source/$synthtool

 

  1. xgxs_sysbus.v for the SYSBUS module;

location: eval/source/$synthtool

 

  1. xgxs_clk_tx.v for the Tx Clk PLL;

location: eval/source/$synthtool

 

  1. xgxs_clk_mx2.v for FPGA/FPSC PLLs;

location: eval/source/$synthtool

 

  1. ring_osc.v  ring oscillator macro black box  to drive um_clk;

location: eval/source

 

  1. xgxs_top_xgmii.v for top-level module that ties all the application components together

location: eval/source/$synthtool

 

 

Files for Place and Route

The gate-level netlist(<ngo>) and the preference/constraint file (<prf>) are located in the: eval/par directories

The ring oscillator “ring_osc.nmc” file is located in the eval/source directory

 

For ispLEVERCORE devices implemented in ORCA4 technology:

        - Netlist file extension is “ngo”

        -Preference file extension is “prf” (PICS Rules File)

 

 

For ispLEVERCORE devices implemented in XPGA technology:

       -Netlist file extension is “ld2”

       -Constraint file extension is “lct”

 

The preference/constraint file (<.prf>) contains information for the ispLEVER Place and Route (PAR) tool and allows for optimum  implementation of this IP Core in the target technology. The supplied preference/constraint file is a good starting point for designs that integrate this IP Core. It may be edited to include the preference/constraint file for additional design components.

 

GUI support in IP Manager for Newly released Core

No configuration of this IP Core using the IP Manager is supported

 

 

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