In order to use a Synplicity or Exemplar generated top-level EDIF 
you must comment and  uncomment the EDIF_DIR line in the script

runpar
runpar.bat

NOTES: 

1. During par some pulsewidth warnings are generated pertaining to the clock driving the DDR cells on both transmit and receive side. These are warnings only and are expected on this design. This warning message will be corrected in a future release of the software.

2. When running trce -hld  72 timing errors are reported pertaining to the DDR. These are expected.
 
3. The route of the Exemplar version reports a total of 3 timing errors
on the preference FREQUENCY NET "clk_156_asb_tx" 156.250000 MHZ. The trce
report will show the same with the total time involved of 109ps. These are expected at this time. These can be corrected by hand editting in the EPIC tool after Place & Routing have been completed.



