Evaluating the XGXS 
======================================

1. Need to unarchive the files ort82g5_work.tar.gz and sysbus_work.tar.gz
in ~eval/lib/modelsim/  to create ort82g5_work/ and sysbus_work/ library directories. These libraries have been compiled using ModelSim V5.6 and should be refreshed if you are using a newer version. This can be done executing the following commands:

vlog -refresh -work sysbus_work
vlog -refresh -work ort82g5_work

sysbus_work   Pre_compiled library for SYSBUS 
ort82g5_work  Pre_compiled library for FPSC (ORT82G5)

2. You may need to also refresh the pre-compiled work library (in this directory) for the xgbe_xgxs_o4_1_001 design. This can be done by executing the following command:

vlog -refresh -work work

work  Pre_compiled library for xgbe_xgxs_o4_1_001 and testbench

Simulation:

1. To run the simulation you need to startup vsim. Do this by typing
   vsim on the command line. You can run the eval typing (at the vsim command prompt:)
		do scripts/run_eval.do

2. During simulation when the files are loading one will get a large number of ERROR messages about debug module .... called from nondebug module. These are expected due to the compilation of source with the -nodebug option for MTI

Files provided:

testbench:

xgxs_top_tb_eval.v
This is the testbench used for this simulation.
The testbench configuration has the xgxs_top_U1 (ORT82G5 FPSC/xgxs core FPGA logic) setup such that its HDOUT is looped back to its HDIN for this test. The device is initialized and then configured to accept data on the XGMII inputs (tx_data,tx_ctrl). This txdata data is generated by the testbench, goes through the bridge and is sent out the HDOUT, looped back to HDIN and is sunk at the internal data frame monitor as well as going out the XGMII out (rx_data). The file eval/tests/test_cmd.v contains the various SMI commands that are issued to accomplish this test. The test consists of a packet stream of a number of CRPAT packets followed by another group of 30 CRPAT packets with 20 errored packets intermixed. Each of these is checked by the internal frame checker and logged in registers which are read through the SMI.(See test_cmd.v below)

tests:

test_cmd.v

This file contains the SMI commands which are used for this test. This explains what registers and bits are being read and written during the test. The test log will report only the register being read or written unless there is an unexpected error at which time it will report 

ERROR -- TESTBENCH: Expected read data=xxxx Received data xxxx at time xxxxxxxx ns


lib/modelsim: (These libraries have been compiled using ModelSim V5.6)

sysbus_work   Pre_compiled library for SYSBUS 
ort82g5_work  Pre_compiled library for FPSC (ORT82G5)

These are created by unzipping the files below

sysbus_work.tar.gz
ort82g5_work.tar.gz
