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Lattice's new ispLeverCORE^TM are large, modular design blocks that can be reused and easily placed within a customer's programmable logic design. ispLeverCORE implement popular industry-standard functions, commonly known as Intellectual Property (IP) cores.

This document contains information to help you evaluate the package you have chosen. The following topics are covered:

General IP Core Information
Evaluation Process
Evaluation Appendix

I. IP Core Information

About the Core

IP Name:	SPI_324P
IP Version:	1.0
IP Configuration Release Date:	March 2004
Configuration Description:	Quad SPI-3 to SPI-4 PHY Layer Bridge IP core, configuration 1
Target Technology:	ORSPI

Software Requirements

Synthesis Tools Supported:	Synplify 7.2 and UP
	Leonardo Spectrum 2003 and UP
Simulation Tool Supported:	ModelSim SE PLUS 5.7c and UP
Lattice Tool Supported:	ispLEVER 4.0 and UP

Installation Procedures

All Lattice IP Cores are available in the zip file format. Unzip the file to the directory location of choice. Refer to the directory structure section for detailed information of the packaged files.

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II. IP Core Evaluation Procedures

Running Functional RTL Simulation

Once the Quad SPI-3 to SPI-4 Bridge core has been downloaded and unzipped to the designated directory, the core is ready for evaluation. The RTL simulation environment contains a testbench and a simple application that uses the Quad SPI-3 to SPI-4 Bridge design. The application instantiates the Quad SPI-3 to SPI-4 Bridge core, an ORCA ORSPI4 module and an ORCA SYSBUS module. The module name of the application is called "orspi_qspi3". The testbench includes a SPI-4 driver, a SPI-4 monitor, an instantiation of the user application and SPI-3 loopback models. In the simulation many packets of varying length generated by the SPI-4 driver are applied to the receive side of the SPI-4 bridge. A loopback is implemented at the SPI-3 interface. The packets received at the SPI-4 transmit interface are checked against the packets sent by the SPI-4 driver .

Simulation Procedures:

The Quad SPI-3 to SPI-4 Link Layer Bridge design and testbench models have been compiled into the work directories “source\top”, source\sim”, and “eval\test\*”. The Quad SPI-3 to SPI-4 PHY IP CORE, ORCA4, ORSPI4 and SYSBUS models have been provided in the directory "lib\modelsim" as zip archives (spi_324p_o4_1_001.zip, orca4_work.zip, orspi4_work.zip and sysbus_work.zip). These files should be unarchived into the directory "lib\modelsim. All these work directories have to be refreshed before simulation can be run. A simulation script file is provided in the "eval\simulation\scripts" directory for RTL simulation.The script file run_vsim.bat uses precompiled models provided with this package. The parameter "MODELTECH" in the script file should be set to the appropriate MTI Modelsim version value for the local system. . The simulation is run by executing “scripts\run_vsim.bat” from the “eval\modelsim” directory. A succesful simulation is achieved when the “TEST PASSED” message is displayed at the end of the simulation.

For more information on how to use ModelSim, please refer to the ModelSim User's Manual.

NOTE: The procedure described above is applicable ONLY when using ModelSim for simulation.

Running Synthesis using Synplicity's Synplify

To synthesize the Quad SPI-3 to SPI-4 PHY Layer Bridge solution Synplicity’s Synplify in one step, Goto to the directory “eval\synthesis\synplicity\” and enter “run_syn.bat”. A top-level EDIF for the application will be produced in the rev_1 directory. Users may use run_syn.bat as a guide and template if they are creating their own unique system-level project solution.

The following step-by-step procedure may also be executed. Note that the step-by step flow results vary from those obtained with the scripted flow due to possible small differences in options between both flows.

Create a new working directory for synthesis.

Launch the Synplify synthesis tool.

Start a new project and add the specified files in the following order:

eval\source\top\qspi3_define.v

eval\source\synplicity\orca4_synplify.v

eval\source\synplicity\rfclk_hpll_ph_bo.v

eval\source\synplicity\rfclk_pll_ph_bo.v

eval\source\synplicity\sysbus_fpsc.v

eval\source\synplicity\mycore.v

eval\source\top\spi_324p_o4_1_001.v

eval\source\top\orspi.v

In the Implementation Options select the ORCA series 4 technology, the O4E06 part, speed grade -2 and package BA352. Note that these options are acceptable since synthesis target the series 4 based FPGA array of the device.

Specify an EDIF netlist filename and EDIF netlist output location in the Implementation Options. This top-level EDIF netlist will be used during Place and Route.

In the Implementation Options, set the following:

- Fanout guide : 1000

- Enable FSM Compiler

- Enable Resource Sharing

- Set the global frequency constraint to 104 MHz.

Select run.

Running Synthesis using LeonardoSpectrum

To synthesize the Quad SPI-3 to SPI-4 PHY Layer Bridge solution using Leonardo Spectrum in one step, go to the directory “eval\synthesis\exemplar\” and enter “run_syn.bat”. A top-level EDIF for the application will be produced. Users may use run_syn.bat as a guide and template if they are creating their own unique system-level project solution.

The step-by-step procedure provided below describes how to run synthesis using Leonardo Spectrum.

Create a new working directory for synthesis.

Launch the Leonardo Spectrum synthesis tool.

Start a new project and select Lattice device technology ORCA-4E.

Select Input tab, set the Working Directory path pointed to the source directory.

Open the specified files in the following order:

eval\source\top\qspi3_define.v

eval\source\exemplar\orca4_leonardo.v

eval\source\exemplar\rfclk_hpll_ph_bo.v

eval\source\exemplar\rfclk_pll_ph_bo.v

eval\source\exemplar\sysbus_fpsc.v

eval\source\exemplar\mycore.v

eval\source\top\spi_324p_o4_1_001.v

eval\source\top\orspi.v

Select orspi,v , use the right click button on your mouse, and choose from the list “Make orspi.v Top of the Design”.

In the Constraints tab, set Clock Frequency as 104 MHz.

Set the synthesis directory, created in step 1, as the path where you would like to save the output netlist.

Specify an EDIF netlist filename for the output file. This top-level EDIF netlist will be used during Place and Route.

Select Run Flow

Running Place and Route (PAR) for ORCA devices in ispLEVER

Once the EDIF netlist is generated, the next step is to map, place and route the design.

The step-by-step procedure provided below explains how to run an EDIF based flow through place and route using ispLever Project Navigator

Once the EDIF netlist is generated, import the EDIF into the Project Navigator. The ispLEVER software

automatically detects the provided EDIF netlist of the instantiated IP core in the design. The step-by-step procedure provided below describes how to perform Place and Route in ispLEVER for an ORCA device:

Create a new working directory for Place and Route.

Start a new project, assign a project name and select the project type as EDIF.

Select the ORSPI4 (or ORSPII if that is the option available) target device, with -2 speed grade and BS1036 package.

Copy the following files to the Place and Route working directory:

a) eval\ngo\spi_324p_o4_1_001.ngo

b) eval\prf\exemplar\orspi_qspi3.prf (with the Leonardo Spectrum EDIF)

eval\prf \synplicity\ orspi_qspi3.prf (with the Synplify EDIF)

c) The top-level EDIF netlist generated from running synthesis

Rename the orspi_qspi3.prf file (in step 4) to match the project name. For example, if the project name is "demo", then the .prf file must be renamed to demo.prf. The preference file name must match that of the project name.

Import the EDIF netlist into the project.

In the ispLEVER Project Navigator, select Tools->Timing Checkpoint Options. The Timing Checkpoint Options window will pop-up. In both Checkpoint Options, select Continue.

In the ispLEVER Project Navigator, highlight Place & Route Design, with a right mouse click select Properties. Set the following Properties:

- Placement Iterations: 1

- Placement Save Best Run: 1

- Placement Iteration Start Point: 4

- Routing Resource Optimization: 1

- Routing Delay Reduction Passes: 1 for Synplify EDIF, 6 for Leonardo EDIF

- Routing Passes: 10

- Placement Effort Level: 5

All other options remain at their default values.

Select the Place & Route Trace Report in the project navigator to execute Place and Route and generate a timing report for ORCA.

Highlight Place & Route TRACE Report, with a right mouse click and select Force One Level. A new timing report is generated.

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III. IP Core Evaluation Appendix

Directory Structure

The directory structure for the Lattice ispLeverCORE^TM is shown below and includes the basic description of the contents.

\ spi_324p_o4_1_001

|--\Readme_o4_1_001.html

|--\orca4

|--\ver1.0

|--\eval (Customer RTL functional simulation directory for evaluation)

|--\gui_script

|--\module_gen

| (Contents: Scripts for IP configuration using IP

| Manager GUI. This directory is present only if

| the IP Manager of the most recent release of the

| ispLEVER software does not contain the released

| IP Core yet.)

|--\models (Contents: this content is empty)

|--\source (Contents: simulation and synthesis source code to support the

| user IP application)

|--\ngo (Contents: Precompiled .ngo file for the evaluation version of the

| IP core)

|--\prf (Contents: .prf file for associated IP Design Core)

|--\simulation (Run/execute functional RTL simulation here.

| Example: scripts/run_vsim.bat)

|--\scripts (Contents: ModelSim macro (*.do) to run

| simulation)

|--\work (Contents: Will contain compiled testbench files

| AFTER running functional RTL simulation)

|--\golden (Contents: Reference data output from simulation used

to compare against customer simulation results)

|--\synthesis (Contents: Scripts for respective synthesis runs)

|--\exemplar

|--\synplicity

|--\testbench (Contents: Testbench for evaluation)

|--\lib

|--\modelsim

|--\ spi_324p_o4_1_001 (Compiled IP Core simulation model)

|--\orspi4_work (Compiled ORSPI4 Core model)

|--\orca4_work (Compiled ORCA4 libraries)

|--\sysbus_work (Compiled ORCA4 SYSTEM BUS libraries)

Files for Synthesis

The Quad SPI-3 to SPI-4 PHY Layer Bridge evaluation package includes the following components:

· Basic Quad SPI-3 to SPI-4 PHY Layer Bridge IP core;

· Verilog module that instantiates the ORSPI4 component and the ORCA4 SYSBUS with User Slave component, providing a Motorola Power PC interface to the IP core’s register interface, as well as registers in the ORSPI4 embedded core;

A set of Verilog files are provided for synthesis. These design files are provided such that this IP Core can be evaluated as a stand-alone device or as part of an application specific design. The files are located in: spi_324p_o4_1_001\eval\source.

This evaluation package is illustrated in Figure 13. The following Verilog files are provided:

qspi3_define.v for the the Quad SPI-3 to SPI-4 PHY Layer Bridge core and top level parameters (Note: this file and all IP parameter files must not be modified in any way. If this file is modified, this IP core may not run at specification);
spi_324p_o4_1_001.v for the Quad SPI-3 to SPI-4 PHY Layer Bridge core;
mycore.v for the ORSPI4 module;
sysbus_fpsc.v for the SYSBUS module;
rfclk_hpll_ph_bo.v for PLL;
rfclk_pll_ph_bo.v for PLL;
orspi.v for "orspi_qspi3" top-level module that ties all the application components together.

Files for Place and Route

The gate-level netlist(<ngo>) and the preference/constraint file (<prf>) are located in the directories: spi_324p_o4_1_001\eval\ngo and spi_324p_o4_1_001\eval\prf respectively.

For ispLEVERCORE devices implemented in ORCA4 technology:

- Netlist file extension is “ngo”

-Preference file extension is “prf” (PICS Rules File)

The preference/constraint file (<.prf>) contains information for the ispLEVER Place and Route (PAR) tool and allows for optimum implementation of this IP Core in the target technology. The supplied preference/constraint file is a good starting point for designs that integrate this IP Core. It may be edited to include the preference/constraint file for additional design components.

GUI support in IP Manager for Newly released Core

If the eval\gui_script is present in this release package, it is because the ispLEVER software does not yet contain the utility that allows for the configuration of this IP Core using the IP Manager. The eval\gui_script\module_gen directory contains a directory of files that allows for the configuration of this IP Core via the IP Manager.

With this directory structure in place, ispLEVER will include the IP Core in the Module/IPManager when opened.

Note: If the gui_script\module_gen.zip file is present in this

release package, it is because the ispLEVER software does not contain the utility that

allows for the configuration of this specific IP module using the Module/IP Manager. The gui_script\module_gen.zip file contains a directory of files that allows for the configuration of this IP module using the Module/IP Manager.

To configure the IP module using the ispLEVER Module/IP Manager:

1. Go to the directory in where the ispLEVER software is installed, for example

C:\ispTOOLS.

2. Unzipped the module_gen.zip file into the \ispcpld folder.

3. If the ispLEVER Project Navigator is open, exit and rerun the tool. The IP module will be included in the list when the Module/IP Manager is run.

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